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Difference between revisions of "hisilicon/kunpeng/hi1616"
< hisilicon‎ | kunpeng

(→‎Cache)
 
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{{hisilicon title|Hi1616}}
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{{hisilicon title|Kunpeng 916 (Hi1616)}}
 
{{chip
 
{{chip
 
|name=Hi1616
 
|name=Hi1616
−
|no image=Yes
+
|image=hi1616 (front).png
 
|designer=HiSilicon
 
|designer=HiSilicon
 
|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
Line 23: Line 23:
 
|max cpus=2
 
|max cpus=2
 
|max memory=512 GiB
 
|max memory=512 GiB
 +
|tdp=85 W
 
}}
 
}}
−
'''Hi1616''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory.
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[[File:hi1616 exhibit sign.jpg|thumb|right|Hi1616 display.]]
 +
'''Kunpeng 916''' ('''Hi1616''') is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz with a TDP of 85 W. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory. This chip supports up to 2-way SMP with two ports supporting 96 Gb/s each.
  
 
== Cache ==
 
== Cache ==
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|l1i break=32x48 KiB
 
|l1i break=32x48 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1d cache=1 KiB
+
|l1d cache=1 MiB
 
|l1d break=32x32 KiB
 
|l1d break=32x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l2 cache=8 MiB
 
|l2 cache=8 MiB
−
|l2 break=32x256 KiB
+
|l2 break=8x1 MiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l3 cache=32 MiB
 
|l3 cache=32 MiB
Line 64: Line 66:
 
|type=PCIe
 
|type=PCIe
 
|pcie revision=3.0
 
|pcie revision=3.0
−
|pcie lanes=16
+
|pcie lanes=46
−
|pcie config=2x8
+
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 
}}
 
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=2
 +
}}
 +
{{expansions entry
 +
|type=SATA
 +
|sata revision=3.0
 +
|sata ports=8
 
}}
 
}}
 +
}}
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=No
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=No
 +
|crc32=Yes
 +
|crypto=No
 +
|fp=No
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
 +
|rdm=No
 +
}}
 +
 
== Utilizing devices ==
 
== Utilizing devices ==
 
* [[used by::HiSilicon D05]]
 
* [[used by::HiSilicon D05]]
 +
* [[used by::Huawei TaiShan 2280]]
 +
  
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{{expand list}}
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<gallery widths=300px heights=200px>
 +
File:hi1616 board 1.jpg
 +
File:hi1616 board 2.jpg
 +
File:hi1616 board 3.jpg
 +
</gallery>

Latest revision as of 09:12, 8 May 2019

Edit Values
Hi1616
hi1616 (front).png
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1616
MarketServer
IntroductionAugust, 2017 (announced)
August, 2017 (launched)
General Specs
FamilyHi16xx
Frequency2,400 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A72
Core NameCortex-A72
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory512 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP85 W
Hi1616 display.

Kunpeng 916 (Hi1616) is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2017. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A72 cores operating at 2.4 GHz with a TDP of 85 W. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory. This chip supports up to 2-way SMP with two ports supporting 96 Gb/s each.

Cache[edit]

Main article: Cortex-A72 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
32x48 KiB8-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem512 GiB
Controllers1
Channels4
Width64 bit
Max Bandwidth71.53 GiB/s
73,246.72 MiB/s
76.805 GB/s
76,804.753 MB/s
0.0699 TiB/s
0.0768 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 46
Configuration: x16, x8, x4
USBRevision: 3.0
Max Ports: 2
SATARevision: 3.0
Max Ports: 8

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices[edit]

  • HiSilicon D05
  • Huawei TaiShan 2280


  • hi1616 board 1.jpg
  • hi1616 board 2.jpg
  • hi1616 board 3.jpg
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1616&oldid=90429"
Facts about "Kunpeng 916 (Hi1616) - HiSilicon"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Kunpeng 916 (Hi1616) - HiSilicon#pcie +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
core count32 +
core nameCortex-A72 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedAugust 2017 +
first launchedAugust 2017 +
full page namehisilicon/kunpeng/hi1616 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateAugust 2017 +
main imageFile:hi1616 (front).png +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels4 +
max sata ports8 +
max usb ports2 +
microarchitectureCortex-A72 +
model numberHi1616 +
nameHi1616 +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
supported memory typeDDR4-2400 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count32 +
used byHiSilicon D05 + and Huawei TaiShan 2280 +
word size64 bit (8 octets, 16 nibbles) +