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Difference between revisions of "intel/xeon gold/6238"
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'''Xeon Gold 6238''' is a {{arch|64}} [[22-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6238 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 140 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. | '''Xeon Gold 6238''' is a {{arch|64}} [[22-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6238 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 140 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. | ||
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+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | The Xeon Gold 6238 features a larger non-default 30.25 MiB of L3, a size that would normally be found on an 22-core part. | ||
+ | {{cache size | ||
+ | |l1 cache=1.25 MiB | ||
+ | |l1i cache=640 KiB | ||
+ | |l1i break=20x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=640 KiB | ||
+ | |l1d break=20x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=20 MiB | ||
+ | |l2 break=20x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=30.25 MiB | ||
+ | |l3 break=22x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 22:23, 7 May 2019
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General Info | |
Microarchitecture |
Xeon Gold 6238 is a 64-bit 22-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6238 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 140 W and features a turbo boost frequency of up to 3.7 GHz.
Cache
- Main article: Cascade Lake § Cache
The Xeon Gold 6238 features a larger non-default 30.25 MiB of L3, a size that would normally be found on an 22-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Gold 6238 - Intel"
full page name | intel/xeon gold/6238 + |
instance of | microprocessor + |
l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) + |
ldate | 1900 + |