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'''Xeon Gold 6226''' is a {{arch|64}} [[dodeca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6226 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
 
'''Xeon Gold 6226''' is a {{arch|64}} [[dodeca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6226 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
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== Cache ==
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{{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Skylake § Cache}}
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The Xeon Gold 6226 features a larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part.
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{{cache size
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|l1 cache=768 KiB
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|l1i cache=384 KiB
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|l1i break=12x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=384 KiB
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|l1d break=12x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=12 MiB
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|l2 break=12x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=19.25 MiB
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|l3 break=14x1.375 MiB
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|l3 desc=11-way set associative
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|l3 policy=write-back
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}}

Revision as of 21:01, 7 May 2019

Edit Values
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General Info
Microarchitecture

Xeon Gold 6226 is a 64-bit dodeca-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6226 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.7 GHz.


Cache

Main article: Skylake § Cache

The Xeon Gold 6226 features a larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
  14x1.375 MiB11-way set associativewrite-back
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