From WikiChip
Difference between revisions of "intel/xeon d/d-1548"
< intel‎ | xeon d

(→‎Expansions)
(→‎Features)
Line 126: Line 126:
 
== Features ==
 
== Features ==
 
{{x86 features
 
{{x86 features
−
| em64t      = Yes
+
|real=Yes
−
| nx          = Yes
+
|protected=Yes
−
| txt        = Yes
+
|smm=Yes
−
| tsx        = Yes
+
|fpu=Yes
−
| ht          = Yes
+
|x8616=Yes
−
| tbt2        = Yes
+
|x8632=Yes
−
| bpt        =  
+
|x8664=Yes
−
| vt-x        = Yes
+
|nx=Yes
−
| vt-d        = Yes
+
|mmx=Yes
−
| mmx        = Yes
+
|emmx=Yes
−
| sse         = Yes
+
|sse=Yes
−
| sse2       = Yes
+
|sse2=Yes
−
| sse3       = Yes
+
|sse3=Yes
−
| ssse3       = Yes
+
|ssse3=Yes
−
| sse4        = Yes
+
|sse41=Yes
−
| sse4.1      = Yes
+
|sse42=Yes
−
| sse4.2      = Yes
+
|sse4a=No
−
| aes         = Yes
+
|avx=Yes
−
| avx        = Yes
+
|avx2=Yes
−
| avx2        = Yes
+
|avx512f=No
−
| bmi        = Yes
+
|avx512cd=No
−
| bmi1        = Yes
+
|avx512er=No
−
| bmi2        = Yes
+
|avx512pf=No
−
| f16c        = Yes
+
|avx512bw=No
−
| fma3        = Yes
+
|avx512dq=No
−
| sgx         =  
+
|avx512vl=No
−
| eist        = Yes
+
|avx512ifma=No
−
| secure key = Yes
+
|avx512vbmi=No
−
| os guard   = Yes
+
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|bmi=Yes
 +
|secure key=Yes
 +
|os guard=Yes
 
}}
 
}}

Revision as of 01:17, 1 April 2019

Edit Values
Xeon D-1548
broadwell de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-1548
Part NumberGG8067402569300
S-SpecSR2DJ
MarketServer, Embedded
IntroductionNovember 1, 2015 (announced)
November 1, 2015 (launched)
Release Price$555.00 (tray)
ShopAmazon
General Specs
FamilyXeon D
SeriesD-1500
LockedYes
Frequency2,000 MHz
Turbo Frequency2,600 MHz (1 core)
Bus typeDMI 2.0
Clock multiplier20
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrangeville
Core NameBroadwell DE
Core Family6
Core Model6
Core SteppingV2
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads16
Max Memory128 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP45 W
OP Temperature0 °C – 108 °C
Packaging
PackageFCBGA-1667 (FCBGA)
Dimension37.5 mm × 37.5 mm × 3.557 mm
Pitch0.7 mm
Contacts1667
broadwell de (back).png

Xeon D-1548 is a 64-bit octa-core x86 microserver SoC introduced by Intel in late 2015. The D-1548 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.0 GHz with a TDP of 45 W and a turbo frequency of 2.6 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.


Cache

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  8x256 KiB8-way set associativewrite-back
L3$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  8x1.5 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem128 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 24
Configuration: x16, x8, x4
PCIeRevision: 2.0
Max Lanes: 8
Configuration: x8, x4
USBRevision: 3.0
Max Ports: 4
USBRevision: 2.0
Max Ports: 4
SATARevision: 3
Max Ports: 6


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 2)

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1548&oldid=87692"
Facts about "Xeon D-1548 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-1548 - Intel#pcie +
back imageFile:broadwell de (back).png +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus typeDMI 2.0 +
clock multiplier20 +
core count8 +
core family6 +
core model6 +
core nameBroadwell DE +
core steppingV2 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon D +
first announcedNovember 1, 2015 +
first launchedNovember 1, 2015 +
full page nameintel/xeon d/d-1548 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel secure key technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description16-way set associative +
l3$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
ldateNovember 1, 2015 +
main imageFile:broadwell de (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max memory131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max operating temperature108 °C +
max sata ports6 +
max usb ports4 +
microarchitectureBroadwell +
min operating temperature0 °C +
model numberD-1548 +
nameXeon D-1548 +
packageFCBGA-1667 +
part numberGG8067402569300 +
platformGrangeville +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 555.00 (€ 499.50, £ 449.55, ¥ 57,348.15) +
release price (tray)$ 555.00 (€ 499.50, £ 449.55, ¥ 57,348.15) +
s-specSR2DJ +
seriesD-1500 +
smp max ways1 +
supported memory typeDDR4-2400 +
tdp45 W (45,000 mW, 0.0603 hp, 0.045 kW) +
technologyCMOS +
thread count16 +
transistor count3,200,000,000 +
turbo frequency (1 core)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +