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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Knights Ferry
+
|name=Rock Creek
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=2009
+
|introduction=December 2009
 
|process=45 nm
 
|process=45 nm
 
|cores=48
 
|cores=48
 
|isa=x86
 
|isa=x86
−
|extension=L1OM
+
|l1i=16 KiB
 +
|l1i per=core
 +
|l1i desc=4-way set associative
 +
|l1d=16 KiB
 +
|l1d per=core
 +
|l1d desc=4-way set associative
 +
|l2=256 KiB
 +
|l2 per=core
 +
|l2 desc=4-way set associative
 +
|l3=16 KiB
 +
|l3 per=tile
 
|predecessor=Polaris
 
|predecessor=Polaris
 
|predecessor link=intel/microarchitectures/polaris
 
|predecessor link=intel/microarchitectures/polaris
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|successor link=intel/microarchitectures/knights ferry
 
|successor link=intel/microarchitectures/knights ferry
 
}}
 
}}
−
'''Rock Creek''' or the ''' Single-Chip Cloud Computer''' ('''SCC''') was the successor to {{\\|Polaris}}, a [[45 nm]] [[many-core]] microarchitecture designed by [[intel]] for high performance computing.
+
'''Rock Creek''' or the ''' Single-Chip Cloud Computer''' ('''SCC''') was the successor to {{\\|Polaris}}, a [[45 nm]] [[many-core]] microarchitecture designed by [[intel]] for high performance computing and many-core software research. The SCC, like {{\\|Polaris}}, was a research project from Intel's [[Tera-scale Computing Research Program]].
 +
 
 +
== Architecture ==
 +
{{empty section}}
 +
 
 +
== Overview ==
 +
[[File:intel scc chip.jpg|right|thumb|SCC Chip]]
 +
{{empty section}}
 +
 
 +
== Rock Lake ==
 +
 
 +
:[[File:rock lake platform.png|700px]]
 +
 
 +
 
 +
:[[File:rock lake platform board.jpg|700px]]
 +
 
 +
== Die ==
 +
* [[45 nm process]]
 +
* 1 poly, 9 Metal (Cu)
 +
* 1,300,000,000 transistors
 +
* 26.5 mm x 21.4 mm
 +
** 567.1 mm² die size
 +
* 1,567 pins LGA packages
 +
** 970 signal pins
 +
 
 +
 
 +
:[[File:rock creek die 2.png|600px]]
 +
 
 +
 
 +
:[[File:rock creek die.png|600px]]
 +
 
 +
 
 +
:[[File:rock creek die 3.png|600px]]
 +
 
 +
 
 +
:[[File:rock creek die (annotated).png|600px]]
 +
 
 +
=== Tile ===
 +
* 48,000,000 transistors
 +
* 3.6 mm x 5.2 mm
 +
** 18.7 mm² silicon area
 +
 
 +
 
 +
:[[File:rock creek tile 2.png|400px]]
 +
 
 +
 
 +
:[[File:rock creek tile 3.png|400px]]
 +
 
 +
 
 +
:[[File:rock creek tile (annotated).png|400px]]
 +
 
 +
=== Additional Shots ===
 +
Additional die and wafer shots provided by Intel:
 +
 
 +
<gallery mode=slideshow>
 +
File:rock creek 1.jpg
 +
File:rock creek 2.jpg
 +
File:rock creek 3.jpg
 +
File:rock creek 4.jpg
 +
</gallery>
 +
 
 +
== Bibliography ==
 +
* [[:File:SCC Sympossium Feb212010 FINAL-A.pdf|“Single-chip Cloud Computer”. An experimental many-core processor from Intel Labs.]] Jim Held, Intel Fellow & Director. Tera-scale Computing Research. Symposium in Santa Clara. 2/12/10.
 +
 
 +
=== Documents ===
 +
* [[:File:SCC Sympossium Dec2010 CHN final.pptx]]
 +
* [[:File:MARC-Symposium-Nov-2010-Stefan-Lankes.pdf|First Experiences with the SCC and a Comparison with Established Architectures]]
 +
* [[:File:RockyLakeHW.pdf|Rocky Lake Hardware (defines LEDs)]]
 +
* [[:File:SCC Platform Overview.pdf|The SCC Platform Overview]]
 +
* [[:File:SCCProgrammersGuide.pdf|The SCC Programmer’s Guide Revision 1.0]]
 +
* [[:File:SCC EAS.pdf|SCC External Architecture Specification (EAS) Revision 1.1]]

Latest revision as of 05:23, 31 March 2019

Edit Values
Rock Creek µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionDecember 2009
Process45 nm
Core Configs48
Instructions
ISAx86
Cache
L1I Cache16 KiB/core
4-way set associative
L1D Cache16 KiB/core
4-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache16 KiB/tile
Succession

Rock Creek or the Single-Chip Cloud Computer (SCC) was the successor to Polaris, a 45 nm many-core microarchitecture designed by intel for high performance computing and many-core software research. The SCC, like Polaris, was a research project from Intel's Tera-scale Computing Research Program.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview[edit]

SCC Chip
New text document.svg This section is empty; you can help add the missing info by editing this page.

Rock Lake[edit]

rock lake platform.png


rock lake platform board.jpg

Die[edit]

  • 45 nm process
  • 1 poly, 9 Metal (Cu)
  • 1,300,000,000 transistors
  • 26.5 mm x 21.4 mm
    • 567.1 mm² die size
  • 1,567 pins LGA packages
    • 970 signal pins


rock creek die 2.png


rock creek die.png


rock creek die 3.png


rock creek die (annotated).png

Tile[edit]

  • 48,000,000 transistors
  • 3.6 mm x 5.2 mm
    • 18.7 mm² silicon area


rock creek tile 2.png


rock creek tile 3.png


rock creek tile (annotated).png

Additional Shots[edit]

Additional die and wafer shots provided by Intel:

  • rock creek 1.jpg
  • rock creek 2.jpg
  • rock creek 3.jpg
  • rock creek 4.jpg

Bibliography[edit]

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/rock_creek&oldid=87470"
Facts about "Rock Creek - Microarchitectures - Intel"
RDF feed
codenameKnights Ferry +
core count48 +
designerIntel +
first launched2009 +
full page nameintel/microarchitectures/rock creek +
instance ofmicroarchitecture +
instruction set architecturex86 +
manufacturerIntel +
microarchitecture typeCPU +
nameKnights Ferry +
process45 nm (0.045 μm, 4.5e-5 mm) +