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Difference between revisions of "samsung/microarchitectures/m4"
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==== Memory subsystem ====
 
==== Memory subsystem ====
 
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== All M3 Processors ==
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{{comp table start}}
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<table class="comptable sortable tc5 tc6 tc7">
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{{comp table header|main|7:List of M4-based Processors}}
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{{comp table header|main|5:Main processor|2:Integrated Graphics}}
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{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency}}
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{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]]
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|?full page name
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|?model number
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|?family
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|?first launched
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|?microarchitecture
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|?core count
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|?base frequency#GHz
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|?integrated gpu
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|?integrated gpu base frequency
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|format=template
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|template=proc table 3
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|userparam=9
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|mainlabel=-
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|valuesep=,
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}}
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{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]]}}
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</table>
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== Bibliography ==
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* LLVM: lib/Target/AArch64/AArch64SchedExynosM4.td

Revision as of 22:41, 13 January 2019

Edit Values
Mongoose 4 µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
Introduction2018
Process8 nm
Instructions
ISAARMv8
Succession

Exynos Mongoose 4 (M4) is the successor to the Mongoose 3, an 8 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology

The M4 is fabricated on Samsung's 8 nm process (8LPP).

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -mcpu=exynos-m4 -mtune=exynos-m4
LLVM -mcpu=exynos-m4 -mtune=exynos-m4


Architecture

The M4 is an incremental microarchitecture that brought a die shrink and minor enhancements.

Key changes from M3

  • 8 nm process (from 10 nm)
  • ARMv8.2 (from ARMv8)
    • Support for full FP16 scalar extension
    • Suppot for integer dot product extension
  • Front end
  • Back end
    • LSU reorganized
    • Floating-point execution units reorganized

This list is incomplete; you can help by expanding it.

Block Diagram

Individual Core

900px

Memory Hierarchy

  • Cache
    • L1I Cache
      • 64 KiB, 4-way set associative
        • 128 B line size
        • per core
      • Parity-protected
    • L1D Cache
      • 64 KiB, 8-way set associative
        • 64 B line size
        • per core
      • 4 cycles for fastest load-to-use
      • 32 B/cycle load bandwidth
      • 16 B/cycle store bandwidth
    • L2 Cache
      • 512 KiB, 8-way set associative
      • Inclusive of L1
      • 12 cycles latency
      • 32 B/cycle bandwidth
    • L3 Cache
      • 4 MiB, 16-way set associative
        • 1 MiB slice/core
      • Exlusive of L2
      • ~37-cycle typical (NUCA)
    • BIU
      • 80 outstanding transactions

Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).

  • TLBs
    • ITLB
      • 512-entry
    • DTLB
      • 32-entry
      • 512-entry Mid-level DTLB
    • STLB
      • 4,096-entry
      • Per core
  • BPU
    • 4K-entry main BTB
    • 128-entry µBTB
    • 64-entry return stack
    • 16K-entry L2 BTB

Core

The core of the M4 is largely the same as M3.

Execution engine

Floating-point cluster

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory subsystem

New text document.svg This section is empty; you can help add the missing info by editing this page.

All M3 Processors

 List of M4-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedArchCoresFrequencyGPUFrequency
Count: 0

Bibliography

  • LLVM: lib/Target/AArch64/AArch64SchedExynosM4.td
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/microarchitectures/m4&oldid=86102"
Facts about "Exynos M4 - Microarchitectures - Samsung"
RDF feed
codenameMongoose 4 +
designerSamsung +
first launched2018 +
full page namesamsung/microarchitectures/m4 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerSamsung +
microarchitecture typeCPU +
nameMongoose 4 +
process8 nm (0.008 μm, 8.0e-6 mm) +