Difference between revisions of "amd/ryzen 3/3200u"

	Edit Values
	Ryzen 3 3200U
	General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	3200U
Part Number	YM3200C4T2OFG
Market	Mobile
Introduction	January 6, 2019 (announced); January 6, 2019 (launched)
Shop	Amazon
	General Specs
Family	Ryzen 3
Series	3000
Frequency	2,600 MHz
Turbo Frequency	3,500 MHz (1 core)
Bus type	PCIe 3.0
Clock multiplier	26
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen+
Core Name	Picasso
Process	12 nm
Transistors	4,940,000,000
Technology	CMOS
Die	209.78 mm²
Word Size	64 bit
Cores	4
Threads	8
Max Memory	64 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	15 W
OP Temperature	0° C – 105 °C
	Packaging
	Unknown package "amd,socket_fp5"

Revision as of 15:12, 7 January 2019

Ryzen 3 3200U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 3200U operates at a base frequency of 2.6 GHz with a TDP of 15 W and a Boost frequency of 3.5 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates Radeon Vega 3 Graphics operating at up to 1.2 GHz.

Cache

Main article: Zen+ § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

192 KiB

196,608 B
0.188 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	4-way set associative
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		2x512 KiB	8-way set associative	write-back

L3$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		1x4 MiB

@@ Line 35: / Line 35: @@
 }}
 '''Ryzen 3 3200U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3200U operates at a base frequency of 2.6 GHz with a [[TDP]] of 15 W and a {{amd|Precision Boost|Boost}} frequency of 3.5 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 3}} Graphics operating at up to 1.2 GHz.
+== Cache ==
+{{main|amd/microarchitectures/zen+#Memory_Hierarchy|l1=Zen+ § Cache}}
+{{cache size
+|l1 cache=192 KiB
+|l1i cache=128 KiB
+|l1i break=2x64 KiB
+|l1i desc=4-way set associative
+|l1d cache=64 KiB
+|l1d break=2x32 KiB
+|l1d desc=8-way set associative
+|l1d policy=write-back
+|l2 cache=1 MiB
+|l2 break=2x512 KiB
+|l2 desc=8-way set associative
+|l2 policy=write-back
+|l3 cache=4 MiB
+|l3 break=1x4 MiB
+}}

base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
bus type	PCIe 3.0 +
clock multiplier	26 +
core count	4 +
core name	Picasso +
designer	AMD +
die area	209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) +
family	Ryzen 3 +
first announced	January 6, 2019 +
first launched	January 6, 2019 +
full page name	amd/ryzen 3/3200u +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	January 6, 2019 +
manufacturer	GlobalFoundries +
market segment	Mobile +
max cpu count	1 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max operating temperature	105 °C +
microarchitecture	Zen+ +
min operating temperature	0° C +
model number	3200U +
name	Ryzen 3 3200U +
part number	YM3200C4T2OFG +
process	12 nm (0.012 μm, 1.2e-5 mm) +
series	3000 +
smp max ways	1 +
tdp	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
technology	CMOS +
thread count	8 +
transistor count	4,940,000,000 +
turbo frequency (1 core)	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 15:12, 7 January 2019

Cache