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Difference between revisions of "amd/ryzen 5/3550h"
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'''Ryzen 5 3550H''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3550H operates at a base frequency of 2.1 GHz with a [[TDP]] of 35 W and a {{amd|Precision Boost|Boost}} frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 8}} Graphics operating at up to 1.2 GHz. | '''Ryzen 5 3550H''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3550H operates at a base frequency of 2.1 GHz with a [[TDP]] of 35 W and a {{amd|Precision Boost|Boost}} frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 8}} Graphics operating at up to 1.2 GHz. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen+#Memory_Hierarchy|l1=Zen+ § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=384 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=4x64 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=4x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=4 MiB | ||
+ | |l3 break=1x4 MiB | ||
+ | }} |
Revision as of 15:11, 7 January 2019
Edit Values | |
Ryzen 5 3550H | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 3550H |
Part Number | YM3500C4T4MFG |
Market | Mobile |
Introduction | January 6, 2019 (announced) January 6, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | 3000 |
Frequency | 2,100 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | PCIe 3.0 |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen+ |
Core Name | Picasso |
Process | 12 nm |
Transistors | 4,940,000,000 |
Technology | CMOS |
Die | 209.78 mm² |
Word Size | 64 bit |
Cores | 4 |
Threads | 8 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 35 W |
OP Temperature | 0° C – 105 °C |
Packaging | |
Unknown package "amd,socket_fp5" |
Ryzen 5 3550H is a 64-bit quad-core mid-range performance x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 3550H operates at a base frequency of 2.1 GHz with a TDP of 35 W and a Boost frequency of 3.7 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates Radeon Vega 8 Graphics operating at up to 1.2 GHz.
Cache
- Main article: Zen+ § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Ryzen 5 3550H - AMD"
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
bus type | PCIe 3.0 + |
clock multiplier | 21 + |
core count | 4 + |
core name | Picasso + |
designer | AMD + |
die area | 209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) + |
family | Ryzen 5 + |
first announced | January 6, 2019 + |
first launched | January 6, 2019 + |
full page name | amd/ryzen 5/3550h + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | January 6, 2019 + |
manufacturer | GlobalFoundries + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max operating temperature | 105 °C + |
microarchitecture | Zen+ + |
min operating temperature | 0° C + |
model number | 3550H + |
name | Ryzen 5 3550H + |
part number | YM3500C4T4MFG + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
series | 3000 + |
smp max ways | 1 + |
tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
technology | CMOS + |
thread count | 8 + |
transistor count | 4,940,000,000 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |