Semiconductor & Computer Engineering
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| process = 90 nm | | process = 90 nm | ||
| process 2 = 65 nm | | process 2 = 65 nm | ||
| + | |isa=x86-32 | ||
| succession = Yes | | succession = Yes | ||
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| predecessor link = intel/microarchitectures/netburst | | predecessor link = intel/microarchitectures/netburst | ||
}} | }} | ||
| − | '''Enhanced NetBurst''' (though no actual name was given by Intel) was a planned [[microarchitecture]] designed to succeed {{\\|NetBurst}}. On May 7 2004, Intel announced that they have cancelled the microarchitecture. | + | '''Enhanced NetBurst''' (though no actual name was given by Intel) was a planned [[microarchitecture]] designed to succeed {{\\|NetBurst}}. On May 7, 2004, Intel announced that they have cancelled the microarchitecture. |
| + | |||
| + | == History == | ||
| + | [[File:tejas cancelled.jpg|right|400px]] | ||
| + | Slated to succeed {{\\|NetBurst}} in the second half of 2004, Intel first demonstrated this microarchitecture in early 2003 with samples expected to reach partners in the second half of the year. Although no actual name was given to the microarchitecture by Intel, at least not publicly, it was expected to feature a considerably longer pipeline over Netburst and thus feature incredibly high clock rates. At IDF in 2003 Intel suggested a clock rate in excess of 5 GHz on the [[90 nm process]] with around 8 to 9 GHz clock rate after a shrink to the [[65 nm process]]. | ||
| + | |||
| + | On May 7, 2004 Intel announced that they've cancelled this microarchitecture and they've moved their multi-core designs forward. The likely culprit is the [[power wall]] and [[memory wall]]. During the announced Paul Otellini (then, president and chief operating officer) confirmed that "thermal considerations" were the root of the problem and that all future Intel processors will be multi-core moving forward. | ||
| + | |||
| + | [[File:after netburst frequency.png|left|550px]] | ||
| + | {{clear}} | ||
| + | |||
| + | == Process Technology == | ||
| + | The Enhanced NetBurst microarchitecture was planned to be manufactured initially on a [[90 nm process]] with faster models after a [[process shrink]] to a [[65 nm process]]. | ||
== Codenames == | == Codenames == | ||
| Line 22: | Line 35: | ||
| {{intel|Jayhawk |l=core}} || Server microprocessors | | {{intel|Jayhawk |l=core}} || Server microprocessors | ||
|} | |} | ||
| + | |||
| + | == Architecture == | ||
| + | This microarchitecture was designed to deliver considerably higher clock speed by elongating the NetBurst's pipeline. | ||
| + | === Key changes from {{\\|NetBurst}} === | ||
| + | * Very long pipeline | ||
| + | ** 40-50+ stages | ||
| + | * Higher clock speeds | ||
| + | ** 5 GHz+ on a [[90 nm process]] | ||
| + | ** 8-9 GHz+ on a [[65 nm process]] | ||
| + | * New Instructions | ||
| + | ** Tejas New Instructions (TNI) (later renamed to {{x86|SSSE3}}) | ||
| + | * Packaging | ||
| + | ** new [[Bumpless Build-Up Layer]] package | ||
| + | * Chipset | ||
| + | ** DDR2 (from DDR) | ||
| + | |||
| + | == References == | ||
| + | * Intel Developer Forums, Spring 2003 | ||
Latest revision as of 06:05, 29 December 2018
| Edit Values | |
| Enhanced NetBurst µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 90 nm, 65 nm |
| Instructions | |
| ISA | x86-32 |
| Succession | |
Enhanced NetBurst (though no actual name was given by Intel) was a planned microarchitecture designed to succeed NetBurst. On May 7, 2004, Intel announced that they have cancelled the microarchitecture.
Contents
History[edit]
Slated to succeed NetBurst in the second half of 2004, Intel first demonstrated this microarchitecture in early 2003 with samples expected to reach partners in the second half of the year. Although no actual name was given to the microarchitecture by Intel, at least not publicly, it was expected to feature a considerably longer pipeline over Netburst and thus feature incredibly high clock rates. At IDF in 2003 Intel suggested a clock rate in excess of 5 GHz on the 90 nm process with around 8 to 9 GHz clock rate after a shrink to the 65 nm process.
On May 7, 2004 Intel announced that they've cancelled this microarchitecture and they've moved their multi-core designs forward. The likely culprit is the power wall and memory wall. During the announced Paul Otellini (then, president and chief operating officer) confirmed that "thermal considerations" were the root of the problem and that all future Intel processors will be multi-core moving forward.
Process Technology[edit]
The Enhanced NetBurst microarchitecture was planned to be manufactured initially on a 90 nm process with faster models after a process shrink to a 65 nm process.
Codenames[edit]
| Codename | Target |
|---|---|
| Tejas | Desktop microprocessors |
| Jayhawk | Server microprocessors |
Architecture[edit]
This microarchitecture was designed to deliver considerably higher clock speed by elongating the NetBurst's pipeline.
Key changes from NetBurst[edit]
- Very long pipeline
- 40-50+ stages
- Higher clock speeds
- 5 GHz+ on a 90 nm process
- 8-9 GHz+ on a 65 nm process
- New Instructions
- Tejas New Instructions (TNI) (later renamed to SSSE3)
- Packaging
- new Bumpless Build-Up Layer package
- Chipset
- DDR2 (from DDR)
References[edit]
- Intel Developer Forums, Spring 2003
| codename | Enhanced NetBurst + |
| designer | Intel + |
| full page name | intel/microarchitectures/enhanced netburst + |
| instance of | microarchitecture + |
| instruction set architecture | x86-32 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Enhanced NetBurst + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |