Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a57"
(a57) |
|||
| Line 12: | Line 12: | ||
}} | }} | ||
'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A15}} === | ||
| + | {{empty section}} | ||
| + | === Block Diagram === | ||
| + | {{empty section}} | ||
| + | === Memory Hierarchy === | ||
| + | {{empty section}} | ||
| + | |||
| + | == Die == | ||
| + | === Samsung [[Exynos 5433]] === | ||
| + | * Samsung [[20 nm process]] | ||
| + | * 113 mm² die size | ||
| + | * Mali-T760 (6 EU) | ||
| + | * Quad-core {{\\|Cortex-A53}} | ||
| + | * Quad-core Cortex-A57 | ||
| + | ** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2 | ||
| + | ** 15.85 mm² per cluster | ||
| + | *** ~3 mm² per core | ||
| + | *** ~3.87 mm² for 2 MiB L2 cache | ||
| + | |||
| + | |||
| + | :[[File:exynos 5433 die.png|600px]] | ||
Revision as of 04:35, 29 December 2018
| Edit Values | |
| Cortex-A57 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | Oct 30, 2012 |
| Succession | |
Cortex-A57 (codename Atlas) is the successor to the Cortex-A15, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.
Contents
Architecture
Key changes from Cortex-A15
 |
This section is empty; you can help add the missing info by editing this page. |
Block Diagram
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
| |
This section is empty; you can help add the missing info by editing this page. |
Die
Samsung Exynos 5433
- Samsung 20 nm process
- 113 mm² die size
- Mali-T760 (6 EU)
- Quad-core Cortex-A53
- Quad-core Cortex-A57
- 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
- 15.85 mm² per cluster
- ~3 mm² per core
- ~3.87 mm² for 2 MiB L2 cache
Facts about "Cortex-A57 - Microarchitectures - ARM"
| codename | Cortex-A57 + |
| designer | ARM Holdings + |
| first launched | October 30, 2012 + |
| full page name | arm holdings/microarchitectures/cortex-a57 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A57 + |