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Difference between revisions of "bitmain/sophon/bm1880"
< bitmain‎ | sophon

(BM1880)
 
 
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|first launched=October 17, 2018
 
|first launched=October 17, 2018
 
|family=Sophon
 
|family=Sophon
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|isa=RV32I
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|isa family=RISC-V
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|isa 2=ARMv8
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|isa 2 family=ARM
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|microarch=Cortex-A53
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|microarch 2=RISC-V
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|core name=Cortex-A53
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|core name 2=RISC-V
 
|technology=CMOS
 
|technology=CMOS
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|max memory=4 GiB
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|v core=0.9 V
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|v io=1.8 V
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|v io 2=3.3 V
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|tdp typical=2.5 W
 
}}
 
}}
 
'''Sophon BM1880''' is a [[neural processor]] designed by [[Bitmain]] launched in [[2018]] for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumption of 2.5 W.
 
'''Sophon BM1880''' is a [[neural processor]] designed by [[Bitmain]] launched in [[2018]] for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumption of 2.5 W.
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== Overview ==
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The BM1880 is a [[neural processor]] designed for edge inference at low power consumption. The chip integrates a single-core [[RISC-V]] MCU subsystem operating at 1 GHz along with a dual-core {{armh|Cortex-A53|l=arch}} application processor operating at 1.5 GHz along with a TPU subsystem by BitMain capable of up to 2 teraOPS (8-bit integer). The chip also includes a capable video subsystem for video and image processing from a camera directly on-chip.
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:[[File:bm1880 block diagram.png|thumb|left|600px|Block Diagram]]
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{{clear}}
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== Memory controller ==
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{{memory controller
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|type=DDR4-3200
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|ecc=No
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|max mem=4 GiB
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|controllers=1
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|channels=2
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|width=32 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=11.92 GiB/s
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}}
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== Video Subsystem ==
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* H.264 Video decoder
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* MJPEG encoder/decoder
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* Video Post Processor
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* 1080P@60fps or 2 channel 1080p@30fps
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== Expansions ==
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* One USB 3.0/USB2.0 host/device
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* Two Integrated GMAC for RGMII/RMII
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* 5xI2C / 16x PWM / 4x UART / Multi GPIO
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== Documents ==
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* [[:File:BM1880 PB V0.07.pdf|Product Brief]]

Latest revision as of 11:19, 25 December 2018

Edit Values
Sophon BM1880
General Info
DesignerBitmain
ManufacturerTSMC
Model NumberBM1880
MarketEdge Compute
IntroductionOctober 17, 2018 (announced)
October 17, 2018 (launched)
General Specs
FamilySophon
Microarchitecture
ISARV32I (RISC-V), ARMv8 (ARM)
MicroarchitectureCortex-A53, RISC-V
Core NameCortex-A53, RISC-V
TechnologyCMOS
Max Memory4 GiB
Electrical
Vcore0.9 V
VI/O1.8 V, 3.3 V
TDP (Typical)2.5 W
Sophon BM1880 is a neural processor designed by Bitmain launched in 2018 for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of 2 TOPS
2,000,000,000,000 OPS
2,000,000,000 KOPS
2,000,000 MOPS
2,000 GOPS
0.002 POPS
(INT8) and a typical power consumption of 2.5 W.

Overview[edit]

The BM1880 is a neural processor designed for edge inference at low power consumption. The chip integrates a single-core RISC-V MCU subsystem operating at 1 GHz along with a dual-core Cortex-A53 application processor operating at 1.5 GHz along with a TPU subsystem by BitMain capable of up to 2 teraOPS (8-bit integer). The chip also includes a capable video subsystem for video and image processing from a camera directly on-chip.


Block Diagram

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Video Subsystem[edit]

  • H.264 Video decoder
  • MJPEG encoder/decoder
  • Video Post Processor
  • 1080P@60fps or 2 channel 1080p@30fps

Expansions[edit]

  • One USB 3.0/USB2.0 host/device
  • Two Integrated GMAC for RGMII/RMII
  • 5xI2C / 16x PWM / 4x UART / Multi GPIO

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=bitmain/sophon/bm1880&oldid=85154"
Facts about "Sophon BM1880 - Bitmain"
RDF feed
core nameCortex-A53 + and RISC-V +
core voltage0.9 V (9 dV, 90 cV, 900 mV) +
designerBitmain +
familySophon +
first announcedOctober 17, 2018 +
first launchedOctober 17, 2018 +
full page namebitmain/sophon/bm1880 +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaRV32I + and ARMv8 +
isa familyRISC-V + and ARM +
ldate3000 +
manufacturerTSMC +
market segmentEdge Compute +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
microarchitectureCortex-A53 + and RISC-V +
model numberBM1880 +
nameSophon BM1880 +
peak integer ops (8-bit)2,000,000,000,000 OPS (2,000,000,000 KOPS, 2,000,000 MOPS, 2,000 GOPS, 2 TOPS, 0.002 POPS, 2.0e-6 EOPS, 2.0e-9 ZOPS) +
supported memory typeDDR4-3200 +
tdp (typical)2.5 W (2,500 mW, 0.00335 hp, 0.0025 kW) +
technologyCMOS +