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Difference between revisions of "cavium/ccpi"
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<tr><th>Lanes/Link</th><td>24</td><td>24</td></tr>
 
<tr><th>Lanes/Link</th><td>24</td><td>24</td></tr>
 
<tr><th>Rate/Link</th><td>30 GB/s<br>240 Gb/s</td><td>75 GB/s<br>600 Gb/s</td></tr>
 
<tr><th>Rate/Link</th><td>30 GB/s<br>240 Gb/s</td><td>75 GB/s<br>600 Gb/s</td></tr>
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<tr><th>BiDir BW/Link</th><td>60 GB/s</td><td>150 GB/s</td></tr>
 
 
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Revision as of 09:16, 16 December 2018

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Cavium Coherent Processor Interconnect (CCPI') is an interconnect architecture designed by Cavium for their microprocessors.

Overview

CCPI is a cache coherent interconnect architecture designed by Cavium for their various microprocessors. CCPI is used to support symmetric multiprocessing on the ThunderX and ThunderX2 families.

Data Rates

 CCPICCPI2
Signaling Rate10 GT/s25 GT/s
Lanes/Link2424
Rate/Link30 GB/s
240 Gb/s		75 GB/s
600 Gb/s


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