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Difference between revisions of "arm holdings/microarchitectures/poseidon"
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== Architecture == | == Architecture == | ||
{{future information}} | {{future information}} | ||
| − | + | === Key changes from {{\\|Ares}} === | |
* [[5 nm process]] (from [[7nm]]) | * [[5 nm process]] (from [[7nm]]) | ||
{{expand list}} | {{expand list}} | ||
Revision as of 17:18, 15 December 2018
| Edit Values | |
| Ares µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Poseidon is the successor to Zeus, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
History
Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
Release Dates
Ares is expected to show up in products around 2021.
Process Technology
Zeus specifically designed takes advantage of the power and area advantages of the 5nm process.
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Key changes from Ares
- 5 nm process (from 7nm)
This list is incomplete; you can help by expanding it.
Bibliography
- Drew Henry keynote, TechCon 2018 keynote.
Facts about "Poseidon - Microarchitectures - ARM"
| codename | Ares + |
| designer | ARM Holdings + |
| full page name | arm holdings/microarchitectures/poseidon + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Ares + |