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− | Exynos 9820 is a 64 | + | {{samsung title|Exynos 9820}} |
− | designed by Samsung | + | {{chip |
− | The processor is fabricated on Samsung's 8 nm LPP (Low Power Plus) FinFET process | + | |name=Exynos 9820 |
− | and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose M4 | + | |image=exynos 9820.png |
− | 2 | + | |designer=Samsung |
− | + | |designer 2=ARM Holdings | |
− | The 9820 incorporates an LTE modem supporting cat 20 | + | |manufacturer=Samsung |
+ | |model number=9820 | ||
+ | |market=Mobile | ||
+ | |first announced=November 14, 2018 | ||
+ | |first launched=January, 2019 | ||
+ | |family=Exynos | ||
+ | |series=Exynos 9 | ||
+ | |frequency= | ||
+ | |frequency 2= | ||
+ | |isa=ARMv8.2 | ||
+ | |isa family=ARM | ||
+ | |isa 2=ARMv8.0 | ||
+ | |isa 2 family=ARM | ||
+ | |microarch=Mongoose M4 | ||
+ | |microarch 2=Cortex-A75 | ||
+ | |microarch 3=Cortex-A55 | ||
+ | |core name=Mongoose M4 | ||
+ | |core name 2=Cortex-A75 | ||
+ | |core name 3=Cortex-A55 | ||
+ | |process=8 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=8 | ||
+ | |thread count=8 | ||
+ | |max cpus=1 | ||
+ | }} | ||
+ | '''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early [[2019]]. The processor is fabricated on Samsung's [[8 nm process]] LPP (Low Power Plus) FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose M4|l=arch}} [[big cores]] and 2 {{armh|Cortex-A55|l=arch}} [[big cores]] and 4 Cortex-A55 [[little cores]]. This chip supports up to 11.6 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a {{armh|Mali-G76}} MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload. | ||
+ | |||
+ | |||
+ | {{unknown features}} | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|samsung/microarchitectures/mongoose_M4#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Mongoose M4 § Cache||l2=Cortex-A76 § Cache}} | ||
+ | For the {{samsung|Mongoose M4|l=arch}} core cluster: | ||
+ | {{cache size | ||
+ | |l1 cache= | ||
+ | |l1i cache= | ||
+ | |l1i break= | ||
+ | |l1i desc= | ||
+ | |l1d cache= | ||
+ | |l1d break= | ||
+ | |l1d desc= | ||
+ | |l2 cache= | ||
+ | |l2 break= | ||
+ | |l2 desc= | ||
+ | |l3 cache= | ||
+ | |l3 break= | ||
+ | }} | ||
+ | |||
+ | For the {{armh|Cortex-A75|l=arch}} cluster: | ||
+ | |||
+ | {{cache size | ||
+ | |l1 cache= | ||
+ | |l1i cache= | ||
+ | |l1i break= | ||
+ | |l1i desc= | ||
+ | |l1d cache= | ||
+ | |l1d break= | ||
+ | |l1d desc= | ||
+ | |l2 cache= | ||
+ | |l2 break= | ||
+ | |l2 desc= | ||
+ | }} | ||
+ | |||
+ | |||
+ | For the {{armh|Cortex-A55|l=arch}} cluster: | ||
+ | |||
+ | {{cache size | ||
+ | |l1 cache= | ||
+ | |l1i cache= | ||
+ | |l1i break= | ||
+ | |l1i desc= | ||
+ | |l1d cache= | ||
+ | |l1d break= | ||
+ | |l1d desc= | ||
+ | |l2 cache= | ||
+ | |l2 break= | ||
+ | |l2 desc= | ||
+ | }} | ||
+ | |||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=LPDDR4X-3600 | ||
+ | |ecc=No | ||
+ | |max mem=11.6 GiB | ||
+ | |controllers=4 | ||
+ | |channels=4 | ||
+ | |width=16 bit | ||
+ | |frequency=1800 MHz | ||
+ | |bandwidth schan= | ||
+ | |bandwidth dchan= | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = Mali-G76 | ||
+ | | device id = | ||
+ | | designer = ARM Holdings | ||
+ | | execution units = 12 | ||
+ | | max displays = 2 | ||
+ | | max memory = | ||
+ | | frequency = 600 MHz | ||
+ | | max frequency = | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = Yes | ||
+ | | output edp = | ||
+ | | output dp = | ||
+ | | output hdmi = | ||
+ | | output vga = | ||
+ | | output dvi = | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | opengl ver = | ||
+ | | opengl es ver = 3.2 | ||
+ | | openvg ver = 1.1 | ||
+ | | opencl ver = 2 | ||
+ | | vulkan ver = 1.0 | ||
+ | | hdmi ver = | ||
+ | | dp ver = | ||
+ | | edp ver = | ||
+ | | max res hdmi = | ||
+ | | max res hdmi freq = | ||
+ | | max res dp = | ||
+ | | max res dp freq = | ||
+ | | max res edp = | ||
+ | | max res edp freq = | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | }} | ||
+ | |||
+ | |||
+ | {| class=wikitable | ||
+ | |- | ||
+ | ! Codec !! Encode !! Decode | ||
+ | |- | ||
+ | | [[HEVC]] (H.265) || {{tchk|yes}} || {{tchk|yes}} | ||
+ | |- | ||
+ | | [[MPEG-4 AVC]] (H.264) || {{tchk|yes}} || {{tchk|yes}} | ||
+ | |- | ||
+ | | [[VP9]] || {{tchk|yes}} || {{tchk|yes}} | ||
+ | |- | ||
+ | |} | ||
+ | |||
+ | All at 4K UHD 150fps. | ||
+ | |||
+ | == Wireless == | ||
+ | {{wireless links | ||
+ | | 2g = | ||
+ | | csd = | ||
+ | | gsm = | ||
+ | | gprs = | ||
+ | | edge = | ||
+ | | cdmaone = | ||
+ | | is-95a = | ||
+ | | is-95b = | ||
+ | | 3g = | ||
+ | | cdma2000 = | ||
+ | | cdma2000 1x = | ||
+ | | cdma2000 1xev-do = | ||
+ | | cdma2000 1x adv = | ||
+ | | umts = | ||
+ | | wcdma = | ||
+ | | td-scdma = | ||
+ | | dc-hsdpa = | ||
+ | | hsdpa = | ||
+ | | hsupa = | ||
+ | | 4g = Yes | ||
+ | | lte a = Yes | ||
+ | | e-utran = | ||
+ | | ue cat dl = 20 | ||
+ | | ue cat dl rate = 2000 Mbps | ||
+ | | ue cat ul = 20 | ||
+ | | ue cat ul rate = 316 Mbps | ||
+ | }} | ||
+ | |||
+ | == ISP == | ||
+ | * 24MP Rear | ||
+ | * 24MP Front | ||
+ | * 16MP+16MP Dual | ||
+ | |||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=No | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=No | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |trustzone=No | ||
+ | |jazelle=No | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | |pmuv3=No | ||
+ | |crc32=Yes | ||
+ | |crypto=Yes | ||
+ | |fp=Yes | ||
+ | |fp16=No | ||
+ | |profile=No | ||
+ | |ras=No | ||
+ | |simd=No | ||
+ | |rdm=No | ||
+ | }} | ||
+ | |||
+ | == Utilizing devices == | ||
+ | * [[used by::Samsung Galaxy S10]] | ||
+ | {{expand list}} |
Revision as of 09:22, 9 December 2018
Edit Values | |
Exynos 9820 | |
200px | |
General Info | |
Designer | Samsung, ARM Holdings |
Manufacturer | Samsung |
Model Number | 9820 |
Market | Mobile |
Introduction | November 14, 2018 (announced) January, 2019 (launched) |
General Specs | |
Family | Exynos |
Series | Exynos 9 |
Microarchitecture | |
ISA | ARMv8.2 (ARM), ARMv8.0 (ARM) |
Microarchitecture | Mongoose M4, Cortex-A75, Cortex-A55 |
Core Name | Mongoose M4, Cortex-A75, Cortex-A55 |
Process | 8 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2019. The processor is fabricated on Samsung's 8 nm process LPP (Low Power Plus) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose M4 big cores and 2 Cortex-A55 big cores and 4 Cortex-A55 little cores. This chip supports up to 11.6 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.
Cache
- Main articles: Mongoose M4 § Cache and Cortex-A76 § Cache
For the Mongoose M4 core cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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|
For the Cortex-A75 cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||
|
For the Cortex-A55 cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Graphics
Integrated Graphics Information
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Codec | Encode | Decode |
---|---|---|
HEVC (H.265) | ✔ | ✔ |
MPEG-4 AVC (H.264) | ✔ | ✔ |
VP9 | ✔ | ✔ |
All at 4K UHD 150fps.
Wireless
Wireless Communications | |||||||
Cellular | |||||||
4G |
|
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ISP
- 24MP Rear
- 24MP Front
- 16MP+16MP Dual
Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Utilizing devices
- Samsung Galaxy S10
This list is incomplete; you can help by expanding it.
- all microprocessor models
- Pages with broken file links
- microprocessor models by samsung
- microprocessor models by samsung based on mongoose m4
- microprocessor models by samsung based on cortex-a75
- microprocessor models by samsung based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on mongoose m4
- microprocessor models by arm holdings based on cortex-a75
- microprocessor models by arm holdings based on cortex-a55
- microprocessor models require attention