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{{pezy title|PEZY-SC}} | {{pezy title|PEZY-SC}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=PEZY-SC |
− | | | + | |image=pezy-sc (front).png |
− | + | |designer=PEZY | |
− | + | |manufacturer=TSMC | |
− | + | |model number=PEZY-SC | |
− | | designer | + | |market=Supercomputer |
− | | manufacturer | + | |first announced=2013 |
− | | model number | + | |first launched=September, 2014 |
− | + | |family=PEZY-SCx | |
− | | market | + | |frequency=733.33 MHz |
− | | first announced | + | |process=28 nm |
− | | first launched | + | |transistors=3,730,000,000 |
− | + | |technology=CMOS | |
− | + | |die area=411.6 mm² | |
− | + | |die length=19.5 mm | |
− | | family | + | |die width=21.1 mm |
− | + | |core count=1,024 | |
− | + | |thread count=8,192 | |
− | | frequency | + | |power=100 W |
− | + | |average power=70 W | |
− | + | |v core=1.0 V | |
− | + | |package module 1={{packages/pezy/fcbga-2112}} | |
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}} | }} | ||
− | '''PEZY-SC''' ('''PEZY Super Computer''') is second generation [[many-core microprocessor]] developed by [[PEZY]] in 2014. | + | '''PEZY-SC''' ('''PEZY Super Computer''') is a second generation [[many-core microprocessor]] developed by [[PEZY]] and introduced in 2014. This chip, which operates at 733 MHz, incorporates 1,024 cores dissipating 100 W. The PEZY-SC powers the [[ZettaScaler]]-1.x series of supercomputers. The PEZY-SC is used in a number of [[TOP500]] & [[Green500]] supercomputers as the world's most efficient supercomputers. |
== Overview == | == Overview == | ||
{{see also|pezy/pezy-1|l1=PEZY-1}} | {{see also|pezy/pezy-1|l1=PEZY-1}} | ||
− | The PEZY-SC (SC for "Super Computer") is [[PEZY]]'s second generation microprocessors which builds upon the {{pezy|PEZY-1}}. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. | + | The PEZY-SC (SC for "Super Computer") is [[PEZY]]'s second generation microprocessors which builds upon the {{pezy|PEZY-1}}. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. The chip contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 1,024 simpler cores supporting 8-way [[simultaneous multithreading|SMT]] for a total of 8,192 [[logical core|threads]]. Operating at 733 MHz, the processor has a peak performance of 3.0 [[TFLOPS]] (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on [[28 nm process|TSMC's 28HPC+]]. |
+ | {{#set: | ||
+ | | peak flops (single-precision) = {{#expr:733333333 * 4 * 1024}} FLOPS | ||
+ | | peak flops (double-precision) = {{#expr:733333333 * 2 * 1024}} FLOPS | ||
+ | }} | ||
+ | The chip has a peak power dissipation of 100 W with a typical power consumption of 70 W which consists of 10 W [[static power|leakage]] + 60 W [[dynamic power|dynamic]]. | ||
In June of 2015, PEZY-SC-based [[supercomputer]]s took all top 3 spots on the [[Green500]] listing as the 3 most efficient supercomputers. PEZY-SC powers [[Shoubu]] (1,181,952 cores, ? kW, 605.624 TFlop/s [[Linpack]] Rmax), and [[Suiren Blue]] (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and [[Suiren]] (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively). | In June of 2015, PEZY-SC-based [[supercomputer]]s took all top 3 spots on the [[Green500]] listing as the 3 most efficient supercomputers. PEZY-SC powers [[Shoubu]] (1,181,952 cores, ? kW, 605.624 TFlop/s [[Linpack]] Rmax), and [[Suiren Blue]] (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and [[Suiren]] (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively). | ||
== Architecture == | == Architecture == | ||
− | The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 | + | {{further|pezy/pezy-scx#Architecture|l1=PEZY-SCx § Architecture}} |
+ | The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$. | ||
[[File:pezy-sc arch.svg|700px]] | [[File:pezy-sc arch.svg|700px]] | ||
− | === | + | == Cache == |
− | + | PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared). | |
− | + | {{cache size | |
+ | |l1 cache=64 KiB | ||
+ | |l1i cache=32 KiB | ||
+ | |l1i break=2x16 KiB | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=2x16 KiB | ||
+ | |l2 cache=64 KiB | ||
+ | |l2 break=1x64 KiB | ||
+ | }} | ||
− | + | The chip integrates a multi-level cache hierarchy: | |
− | + | {{cache size | |
− | + | |l1 cache=3 MiB | |
− | | | + | |l1i cache=2 MiB |
− | | | + | |l1i break=1024x2 KiB |
− | | | + | |l1i desc=per processor element |
− | | | + | |l1d cache=1 MiB |
− | |l2 cache=4 | + | |l1d break=512x2 KiB |
− | |l2 break= | + | |l1d desc=per 2 processor elements |
− | |l2 desc= | + | |l1d policy= |
− | |l2 | + | |l2 cache=4 MiB |
− | |l3 cache=8 | + | |l2 break=4x2 MiB |
− | |l3 desc= | + | |l2 desc=per city |
+ | |l2 policy=write-back | ||
+ | |l3 cache=8 MiB | ||
+ | |l3 break=4x2 MiB | ||
+ | |l3 desc=per prefecture | ||
+ | |l3 policy= | ||
}} | }} | ||
+ | |||
+ | Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE. | ||
== Memory controller == | == Memory controller == | ||
− | {{ | + | {{memory controller |
− | | type | + | |type=DDR4-2133 |
− | | controllers | + | |ecc=Yes |
− | | channels | + | |controllers=8 |
− | | | + | |channels=8 |
− | | bandwidth schan | + | |width=64 bit |
− | | bandwidth dchan | + | |max bandwidth=127.156 GiB/s |
− | | bandwidth qchan | + | |bandwidth schan=15.89 GiB/s |
− | | bandwidth | + | |bandwidth dchan=31.79 GiB/s |
− | | | + | |bandwidth qchan=63.58 GiB/ |
+ | |bandwidth hchan=95.37 GiB/s | ||
+ | |bandwidth ochan=127.156 GiB/s | ||
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions main |
− | | | + | | |
− | | | + | {{expansions entry |
− | | pcie | + | |type=PCIe |
− | | pcie | + | |pcie revision=2.0 |
− | | pcie config | + | |pcie lanes=32 |
− | + | |pcie config=4x8 | |
− | + | }} | |
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}} | }} | ||
+ | |||
+ | == Die Shot == | ||
+ | * [[28 nm process]] | ||
+ | * 19.5 mm × 21.1 mm | ||
+ | * 411.6 mm² die size | ||
+ | |||
+ | :[[File:pezy sc die shot.jpg|650px]] | ||
+ | |||
+ | |||
+ | :[[File:pezy-sc die shot (annotated).png|650px]] | ||
+ | |||
+ | === Floorplan === | ||
+ | |||
+ | :[[File:pezy-sc floorplan.png|650px]] | ||
== External Links == | == External Links == | ||
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* [https://www.top500.org/system/178542 Shoubu Supercomputer on TOP500] | * [https://www.top500.org/system/178542 Shoubu Supercomputer on TOP500] | ||
* [https://www.top500.org/system/178540 Suiren Blue on TOP500] | * [https://www.top500.org/system/178540 Suiren Blue on TOP500] | ||
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Latest revision as of 11:14, 22 September 2018
Edit Values | ||||||||||
PEZY-SC | ||||||||||
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General Info | ||||||||||
Designer | PEZY | |||||||||
Manufacturer | TSMC | |||||||||
Model Number | PEZY-SC | |||||||||
Market | Supercomputer | |||||||||
Introduction | 2013 (announced) September, 2014 (launched) | |||||||||
General Specs | ||||||||||
Family | PEZY-SCx | |||||||||
Frequency | 733.33 MHz | |||||||||
Microarchitecture | ||||||||||
Process | 28 nm | |||||||||
Transistors | 3,730,000,000 | |||||||||
Technology | CMOS | |||||||||
Die | 411.6 mm² 19.5 mm × 21.1 mm | |||||||||
Cores | 1,024 | |||||||||
Threads | 8,192 | |||||||||
Electrical | ||||||||||
Power dissipation | 100 W | |||||||||
Power dissipation (average) | 70 W | |||||||||
Vcore | 1.0 V | |||||||||
Packaging | ||||||||||
|
PEZY-SC (PEZY Super Computer) is a second generation many-core microprocessor developed by PEZY and introduced in 2014. This chip, which operates at 733 MHz, incorporates 1,024 cores dissipating 100 W. The PEZY-SC powers the ZettaScaler-1.x series of supercomputers. The PEZY-SC is used in a number of TOP500 & Green500 supercomputers as the world's most efficient supercomputers.
Contents
Overview[edit]
- See also: PEZY-1
The PEZY-SC (SC for "Super Computer") is PEZY's second generation microprocessors which builds upon the PEZY-1. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. The chip contains 2 ARM926 cores (ARMv5TEJ) along with 1,024 simpler cores supporting 8-way SMT for a total of 8,192 threads. Operating at 733 MHz, the processor has a peak performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's 28HPC+.
The chip has a peak power dissipation of 100 W with a typical power consumption of 70 W which consists of 10 W leakage + 60 W dynamic.
In June of 2015, PEZY-SC-based supercomputers took all top 3 spots on the Green500 listing as the 3 most efficient supercomputers. PEZY-SC powers Shoubu (1,181,952 cores, ? kW, 605.624 TFlop/s Linpack Rmax), and Suiren Blue (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and Suiren (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively).
Architecture[edit]
- Further information: PEZY-SCx § Architecture
The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$.
Cache[edit]
PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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The chip integrates a multi-level cache hierarchy:
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.
Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Die Shot[edit]
- 28 nm process
- 19.5 mm × 21.1 mm
- 411.6 mm² die size
Floorplan[edit]
External Links[edit]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC - PEZY#package + and PEZY-SC - PEZY#pcie + |
base frequency | 733.33 MHz (0.733 GHz, 733,330 kHz) + |
core count | 1,024 + |
core voltage | 1 V (10 dV, 100 cV, 1,000 mV) + |
designer | PEZY + |
die area | 411.6 mm² (0.638 in², 4.116 cm², 411,600,000 µm²) + |
die length | 19.5 mm (1.95 cm, 0.768 in, 19,500 µm) + |
die width | 21.1 mm (2.11 cm, 0.831 in, 21,100 µm) + |
family | PEZY-SCx + |
first announced | 2013 + |
first launched | September 2014 + |
full page name | pezy/pezy-scx/pezy-sc + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) + |
l1d$ description | per 2 processor elements + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | per processor element + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ description | per city + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | per prefecture + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | September 2014 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Supercomputer + |
max memory bandwidth | 127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) + |
max memory channels | 8 + |
model number | PEZY-SC + |
name | PEZY-SC + |
package | FCBGA-2112 + |
peak flops (double-precision) | 1,501,866,665,984 FLOPS (1,501,866,665.984 KFLOPS, 1,501,866.666 MFLOPS, 1,501.867 GFLOPS, 1.502 TFLOPS, 0.0015 PFLOPS, 1.501867e-6 EFLOPS, 1.501867e-9 ZFLOPS) + |
peak flops (single-precision) | 3,003,733,331,968 FLOPS (3,003,733,331.968 KFLOPS, 3,003,733.332 MFLOPS, 3,003.733 GFLOPS, 3.004 TFLOPS, 0.003 PFLOPS, 3.003733e-6 EFLOPS, 3.003733e-9 ZFLOPS) + |
power dissipation | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
power dissipation (average) | 70 W (70,000 mW, 0.0939 hp, 0.07 kW) + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
supported memory type | DDR4-2133 + |
technology | CMOS + |
thread count | 8,192 + |
transistor count | 3,730,000,000 + |