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Difference between revisions of "nvidia/microarchitectures/carmel"
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|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
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|isa=ARMv8 | |isa=ARMv8 | ||
|feature=RAS | |feature=RAS | ||
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|l3=4 MiB | |l3=4 MiB | ||
|l3 per=complex | |l3 per=complex | ||
| − | |predecessor= | + | |predecessor=Denver 2 |
| − | |predecessor link= | + | |predecessor link=nvidia/microarchitectures/denver 2 |
}} | }} | ||
| + | Carmel is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]]. | ||
| + | |||
| + | == Architecture == | ||
| + | Nvidia disclosed very few details regarding Carmel. | ||
| + | |||
| + | * [[12 nm]] (12FF) | ||
| + | * ARMv8.2 (Only AArch64) | ||
| + | ** ARM RAS standard support | ||
| + | * Eight-core cluster | ||
| + | ** 4x Core duplexes | ||
| + | |||
| + | === Memory Hierarchy === | ||
| + | * Cache | ||
| + | ** L1 | ||
| + | ** L2 | ||
| + | *** 2 MiB | ||
| + | **** Shared per duplex | ||
| + | ** L3 | ||
| + | *** 4 MiB | ||
| + | **** Shared by entire cluster | ||
| + | **** Exclusive | ||
| + | |||
| + | == Bibliography == | ||
| + | * IEEE Hot Chips 30 Symposium (HCS) 2018. | ||
Revision as of 09:55, 30 August 2018
| Edit Values | |
| Carmel µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Introduction | January 7, 2018 |
| Process | 12 nm |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L2 Cache | 2 MiB/cluster |
| L3 Cache | 4 MiB/complex |
| Succession | |
Carmel is a the successor to Denver 2, an ARM microarchitecture for Nvidia's Tegra series of SoCs.
Architecture
Nvidia disclosed very few details regarding Carmel.
- 12 nm (12FF)
- ARMv8.2 (Only AArch64)
- ARM RAS standard support
- Eight-core cluster
- 4x Core duplexes
Memory Hierarchy
- Cache
- L1
- L2
- 2 MiB
- Shared per duplex
- 2 MiB
- L3
- 4 MiB
- Shared by entire cluster
- Exclusive
- 4 MiB
Bibliography
- IEEE Hot Chips 30 Symposium (HCS) 2018.
Facts about "Carmel - Microarchitectures - Nvidia"
| codename | Carmel + |
| core count | 8 + |
| designer | Nvidia + |
| first launched | January 7, 2018 + |
| full page name | nvidia/microarchitectures/carmel + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Carmel + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |