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Difference between revisions of "intel/core m/m3-6y30"
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− | {{intel title|Core | + | {{intel title|Core m3-6Y30}} |
− | {{ | + | {{chip |
− | | name | + | |name=Core m3-6Y30 |
− | | | + | |image=skylake y (front).png |
− | + | |image size=250px | |
− | | image size | + | |designer=Intel |
− | + | |manufacturer=Intel | |
− | | designer | + | |model number=m3-6Y30 |
− | | manufacturer | + | |part number=HE8066201930521 |
− | | model number | + | |s-spec=SR2EN |
− | | part number | + | |market=Mobile |
− | | market | + | |first announced=September 1, 2015 |
− | | first announced | + | |first launched=September 27, 2015 |
− | | first launched | + | |release price=$281 |
− | + | |family=Core m3 | |
− | + | |series=m-6Y | |
− | | release price | + | |locked=Yes |
− | + | |frequency=900 MHz | |
− | | family | + | |turbo frequency1=2,200 MHz |
− | | series | + | |turbo frequency2=2,000 MHz |
− | | locked | + | |turbo frequency=Yes |
− | | frequency | + | |bus type=DMI 3.0 |
− | | turbo | + | |clock multiplier=9 |
− | | turbo | + | |isa=x86-64 |
− | | turbo | + | |isa family=x86 |
− | | bus type | + | |microarch=Skylake |
− | + | |platform=Skylake | |
− | + | |core name=Skylake Y | |
− | | clock multiplier | + | |core family=6 |
− | | | + | |core model=78 |
− | + | |core stepping=D1 | |
− | + | |process=14 nm | |
− | + | |transistors=1,750,000,000 | |
− | + | |technology=CMOS | |
− | | isa family | + | |die area=98.57 mm² |
− | + | |die length=10.3 mm | |
− | | microarch | + | |die width=9.57 mm |
− | | platform | + | |mcp=Yes |
− | + | |die count=2 | |
− | | core name | + | |word size=64 bit |
− | | core family | + | |core count=2 |
− | | core model | + | |thread count=4 |
− | | core stepping | + | |max cpus=1 |
− | | process | + | |max memory=16 GiB |
− | | transistors | + | |sdp=3 W |
− | | technology | + | |tdp=4.5 W |
− | | die area | + | |ctdp down=3.8 W |
− | | die width | + | |ctdp down frequency=600 MHz |
− | | die | + | |ctdp up=7 W |
− | | word size | + | |ctdp up frequency=1500 MHz |
− | | core count | + | |tjunc min=5 °C |
− | | thread count | + | |tjunc max=100 °C |
− | | max cpus | + | |package name 1=intel,fcbga_1515 |
− | | max memory | ||
− | |||
− | |||
− | |||
− | |||
− | | sdp | ||
− | | tdp | ||
− | | ctdp down | ||
− | | ctdp down frequency = 600 MHz | ||
− | | ctdp up | ||
− | | ctdp up frequency | ||
− | | tjunc min | ||
− | | tjunc max | ||
− | |||
− | | package | ||
}} | }} | ||
'''Core M3-6Y30''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 900 MHz with a max turbo frequency of 2.2 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M3-6Y30 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 850 MHz. | '''Core M3-6Y30''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 900 MHz with a max turbo frequency of 2.2 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M3-6Y30 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 850 MHz. | ||
Line 92: | Line 77: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=LPDDR3-1866 | + | |type=LPDDR3-1866 |
+ | |type 2=DDR3L-1600 | ||
|ecc=No | |ecc=No | ||
|max mem=16 GiB | |max mem=16 GiB | ||
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|sse42=Yes | |sse42=Yes | ||
|sse4a=No | |sse4a=No | ||
− | |avx= | + | |avx=Yes |
− | |avx2= | + | |avx2=Yes |
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 194: | Line 180: | ||
|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=Yes |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
Line 206: | Line 192: | ||
|sipp=No | |sipp=No | ||
|att=No | |att=No | ||
− | |ipt= | + | |ipt=No |
|tsx=No | |tsx=No | ||
|txt=No | |txt=No | ||
Line 214: | Line 200: | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=Yes |
|sgx=Yes | |sgx=Yes | ||
|securekey=Yes | |securekey=Yes | ||
− | |osguard= | + | |osguard=Yes |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 224: | Line 210: | ||
|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No |
Latest revision as of 16:58, 28 August 2018
Edit Values | |
Core m3-6Y30 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | m3-6Y30 |
Part Number | HE8066201930521 |
S-Spec | SR2EN |
Market | Mobile |
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) |
Release Price | $281 |
Shop | Amazon |
General Specs | |
Family | Core m3 |
Series | m-6Y |
Locked | Yes |
Frequency | 900 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 2,200 MHz (1 core), 2,000 MHz (2 cores) |
Bus type | DMI 3.0 |
Clock multiplier | 9 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake |
Platform | Skylake |
Core Name | Skylake Y |
Core Family | 6 |
Core Model | 78 |
Core Stepping | D1 |
Process | 14 nm |
Transistors | 1,750,000,000 |
Technology | CMOS |
Die | 98.57 mm² 10.3 mm × 9.57 mm |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 2 |
Threads | 4 |
Max Memory | 16 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
SDP | 3 W |
TDP | 4.5 W |
cTDP down | 3.8 W |
cTDP down frequency | 600 MHz |
cTDP up | 7 W |
cTDP up frequency | 1500 MHz |
Tjunction | 5 °C – 100 °C |
Packaging | |
Package | FCBGA-1515 (BGA) |
Dimension | 20 mm × 16.5 mm × 0.5 mm |
Pitch | 0.4 mm |
Contacts | 1515 |
Core M3-6Y30 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 900 MHz with a max turbo frequency of 2.2 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M3-6Y30 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 850 MHz.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Drivers[edit]
Facts about "Core m3-6Y30 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core m3-6Y30 - Intel#io + |
base frequency | 900 MHz (0.9 GHz, 900,000 kHz) + |
bus type | DMI 3.0 + |
clock multiplier | 9 + |
core count | 2 + |
core family | 6 + |
core model | 78 + |
core name | Skylake Y + |
core stepping | D1 + |
designer | Intel + |
device id | 0x191E + |
die area | 98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) + |
die count | 2 + |
die length | 10.3 mm (1.03 cm, 0.406 in, 10,300 µm) + |
die width | 9.57 mm (0.957 cm, 0.377 in, 9,570 µm) + |
drivers url | https://downloadcenter.intel.com/product/94027 + |
family | Core m3 + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
full page name | intel/core m/m3-6y30 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 515 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | September 27, 2015 + |
main image | + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max memory bandwidth | 27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 10 + |
microarchitecture | Skylake + |
min junction temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
model number | m3-6Y30 + |
name | Core m3-6Y30 + |
package | FCBGA-1515 + |
part number | HE8066201930521 + |
platform | Skylake + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) + |
s-spec | SR2EN + |
sdp | 3 W (3,000 mW, 0.00402 hp, 0.003 kW) + |
series | m-6Y + |
smp max ways | 1 + |
supported memory type | LPDDR3-1866 + and DDR3L-1600 + |
tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
tdp down | 3.8 W (3,800 mW, 0.0051 hp, 0.0038 kW) + |
tdp down frequency | 600 MHz (0.6 GHz, 600,000 kHz) + |
tdp up | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
tdp up frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 1,750,000,000 + |
turbo frequency (1 core) | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
turbo frequency (2 cores) | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |