From WikiChip
Difference between revisions of "amd/ryzen threadripper/2950x"
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| + | == Cache == | ||
| + | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=1.5 MiB | ||
| + | |l1i cache=1 MiB | ||
| + | |l1i break=16x64 KiB | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1d cache=512 KiB | ||
| + | |l1d break=16x32 KiB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d policy=write-back | ||
| + | |l2 cache=8 MiB | ||
| + | |l2 break=16x512 KiB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 policy=write-back | ||
| + | |l3 cache=64 MiB | ||
| + | |l3 break=8x8 MiB | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
| + | }} | ||
Revision as of 10:16, 29 July 2018
| Edit Values | |
| Ryzen Threadripper 2950X | |
| General Info | |
| Designer | AMD |
| Manufacturer | GlobalFoundries |
| Model Number | 2950X |
| Market | Desktop |
| Introduction | August, 2018 (announced) August, 2018 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Ryzen Threadripper |
| Series | Ryzen |
| Locked | No |
| Frequency | 3,100 MHz |
| Bus rate | 4 × 8 GT/s |
| Clock multiplier | 31 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Zen+ |
| Core Family | 23 |
| Process | 12 nm |
| Technology | CMOS |
| Die | 213 mm² |
| MCP | Yes (4 dies) |
| Word Size | 64 bit |
| Cores | 16 |
| Threads | 32 |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| TDP | 125 W |
Ryzen Threadripper 2950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by AMD in mid-2018. The 2950X, which is based on their Zen+ microarchitecture, is fabricated on a 12 nm process. The 2950X operates at a base frequency of 3.1 GHz with a TDP of 125 W.
Cache
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Ryzen Threadripper 2950X - AMD"
| base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| clock multiplier | 31 + |
| core count | 16 + |
| core family | 23 + |
| designer | AMD + |
| die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
| die count | 4 + |
| family | Ryzen Threadripper + |
| first announced | August 2018 + |
| first launched | August 2018 + |
| full page name | amd/ryzen threadripper/2950x + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| is multi-chip package | true + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
| ldate | 3000 + |
| manufacturer | GlobalFoundries + |
| market segment | Desktop + |
| max cpu count | 1 + |
| microarchitecture | Zen+ + |
| model number | 2950X + |
| name | Ryzen Threadripper 2950X + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |
| series | Ryzen + |
| smp max ways | 1 + |
| tdp | 125 W (125,000 mW, 0.168 hp, 0.125 kW) + |
| technology | CMOS + |
| thread count | 32 + |
| word size | 64 bit (8 octets, 16 nibbles) + |