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Difference between revisions of "intel/core m/m3-8100y"
< intel‎ | core m

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|series=M3-8000
 
|series=M3-8000
 
|locked=Yes
 
|locked=Yes
−
|frequency=1,600 MHz
+
|frequency=1,100 MHz
 +
|turbo frequency1=3,400 MHz
 +
|turbo frequency2=2,700 MHz
 
|bus type=OPI
 
|bus type=OPI
 
|bus rate=4 GT/s
 
|bus rate=4 GT/s

Revision as of 20:34, 15 July 2018

Edit Values
M3-8100Y
General Info
DesignerIntel
ManufacturerIntel
Model NumberM3-8100Y
MarketMobile
ShopAmazon
General Specs
FamilyCore M3
SeriesM3-8000
LockedYes
Frequency1,100 MHz
Turbo Frequency3,400 MHz (1 core),
2,700 MHz (2 cores)
Bus typeOPI
Bus rate4 GT/s
Clock multiplier16
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureAmber Lake
ChipsetCannon Point
Core NameAmber Lake Y
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP4.5 W

Core M3-8100Y is a 64-bit dual-core low-end performance ultra-low power x86 mobile microprocessor expected to be introduced by Intel in 2018. This chip, which is based on the Amber Lake microarchitecture, is fabricated on Intel's 14 nm process. The M3-8100Y operates at 1.6 GHz with a TDP of 4.5 W. The processor supports up to 16 GiB of dual-channel ? memory and incorporates Intel's UHD Graphics 615 IGP operating at ? MHz with a burst frequency of ? MHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Amber Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes10
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUUHD Graphics 615
DesignerIntel
Execution Units24Max Displays3
Max Memory16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency? MHz
"? MHz" is not a number.
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.4
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m3-8100y&oldid=80432"
Facts about "Core M3-8100Y - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core M3-8100Y - Intel#io +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus typeOPI +
chipsetCannon Point +
clock multiplier16 +
core count2 +
core family6 +
core nameAmber Lake Y +
designerIntel +
familyCore M3 +
full page nameintel/core m/m3-8100y +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuUHD Graphics 615 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description16-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate3000 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes10 +
microarchitectureAmber Lake +
model numberM3-8100Y +
nameM3-8100Y +
process14 nm (0.014 μm, 1.4e-5 mm) +
seriesM3-8000 +
smp max ways1 +
tdp4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)3,400 MHz (3.4 GHz, 3,400,000 kHz) +
turbo frequency (2 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +