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Difference between revisions of "baidu/kunlun"
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== Overview == | == Overview == | ||
− | Baidu initially started development of {{baidu|XPU|the architecture|l=arch}} in [[2011]]. All initial research and development were done on [[FPGAs]]. In July [[2018]], Baidu announced that they have designed a physical chip based on the same architecture. | + | Baidu initially started development of {{baidu|XPU|the architecture|l=arch}} in [[2011]]. All initial research and development were done on [[FPGAs]]. In July [[2018]], Baidu announced that they have designed a physical chip based on the same architecture. The new chips are designed for high-performance [[cloud]], [[edge]], and [[autonomous vehicles]] applications. |
== Models == | == Models == | ||
{{empty section}} | {{empty section}} |
Latest revision as of 00:25, 5 July 2018
Kunlun | |
Developer | Baidu |
Manufacturer | Samsung |
Type | Neural Processors |
Introduction | July 3, 2018 (announced) |
Architecture | Many tiny cores architecture |
µarch | XPU |
Process | 14 nm 0.014 μm
1.4e-5 mm |
Technology | CMOS |
Kunlun is a series of neural processors designed by Baidu for the cloud, edge, and autonomous vehicles.
Overview[edit]
Baidu initially started development of the architecture in 2011. All initial research and development were done on FPGAs. In July 2018, Baidu announced that they have designed a physical chip based on the same architecture. The new chips are designed for high-performance cloud, edge, and autonomous vehicles applications.
Models[edit]
This section is empty; you can help add the missing info by editing this page. |
Facts about "Kunlun - Baidu"
designer | Baidu + |
first announced | July 3, 2018 + |
full page name | baidu/kunlun + |
instance of | integrated circuit family + |
main designer | Baidu + |
manufacturer | Samsung + |
microarchitecture | XPU + |
name | Kunlun + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |