From WikiChip
Difference between revisions of "cavium/thunderx2/cn9978"
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|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
|bandwidth ochan=158.95 GiB/s | |bandwidth ochan=158.95 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=56 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | |pcie config 4=x1 | ||
+ | }} | ||
}} | }} |
Revision as of 00:26, 25 June 2018
Edit Values | |
ThunderX2 CN9978 | |
General Info | |
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN9978 |
Part Number | CN9978-2300LG4077-Y21-G, CN9978-2200LG4077-Y21-G, CN9978-2100LG4077-Y21-G, CN9978-2000LG4077-Y21-G, CN9978-1800LG4077-Y21-G |
Market | Server |
Introduction | May 7, 2018 (announced) May 7, 2018 (launched) |
General Specs | |
Family | ThunderX2 |
Frequency | 1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz |
Microarchitecture | |
ISA | ARMv8.1 (ARM) |
Microarchitecture | Vulcan |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 30 |
Threads | 120 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Packaging | |
Package | FCLGA-4077 (LGA) |
Contacts | 4077 |
ThunderX2 CN9978 is a 64-bit triaconta-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9978 operates between 1.8 GHz and 2.3 GHz and supports up to quad/octa-channel DDR4-2666 memory.
Cache
- Main article: Vulcan § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Facts about "ThunderX2 CN9978 - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | ThunderX2 CN9978 - Cavium#pcie + |
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) +, 2,100 MHz (2.1 GHz, 2,100,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
core count | 30 + |
designer | Cavium + |
family | ThunderX2 + |
first announced | May 7, 2018 + |
first launched | May 7, 2018 + |
full page name | cavium/thunderx2/cn9978 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8.1 + |
isa family | ARM + |
l1$ size | 1,914.88 KiB (1,960,837.12 B, 1.87 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 960 KiB (983,040 B, 0.938 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 960 KiB (983,040 B, 0.938 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 7.5 MiB (7,680 KiB, 7,864,320 B, 0.00732 GiB) + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |
ldate | May 7, 2018 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
microarchitecture | Vulcan + |
model number | CN9978 + |
name | ThunderX2 CN9978 + |
package | FCLGA-4077 + |
part number | CN9978-2300LG4077-Y21-G +, CN9978-2200LG4077-Y21-G +, CN9978-2100LG4077-Y21-G +, CN9978-2000LG4077-Y21-G + and CN9978-1800LG4077-Y21-G + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
smp max ways | 2 + |
supported memory type | DDR4-2666 + |
technology | CMOS + |
thread count | 120 + |
word size | 64 bit (8 octets, 16 nibbles) + |