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Difference between revisions of "graphcore/microarchitectures/colossus"
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* ~800 mm² die size | * ~800 mm² die size | ||
* 23,647,173,309 transistors | * 23,647,173,309 transistors | ||
− | * 1,216 | + | * 1,216 PUs |
+ | ** 2 Grids of 608 PUs each | ||
+ | *** 8 x 19 blocks | ||
+ | **** 4 PUs / block | ||
** 300 MiB on-die memory | ** 300 MiB on-die memory | ||
+ | |||
:[[File:colossus floorplan.png|500px]] | :[[File:colossus floorplan.png|500px]] | ||
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+ | :[[File:colossus floorplan (annotated).png|500px]] |
Latest revision as of 02:40, 24 June 2018
Edit Values | |
Colossus µarch | |
General Info | |
Arch Type | NPU |
Designer | Graphcore |
Manufacturer | TSMC |
Introduction | 2018 |
Process | 16 nm |
Colossus is a 16 nm microarchitecture for high-performance neural processors designed by Graphcore set to be introduced in late-2018.
Etymology[edit]
Codename Colossus was chosen in honor of Tommy Flowers and the Colossus computer.
Process Technology[edit]
Colossus is designed to be fabricated on TSMC's 16 nm FinFET process.
Architecture[edit]
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Die[edit]
Floorplan[edit]
- 16 nm process
- ~800 mm² die size
- 23,647,173,309 transistors
- 1,216 PUs
- 2 Grids of 608 PUs each
- 8 x 19 blocks
- 4 PUs / block
- 8 x 19 blocks
- 300 MiB on-die memory
- 2 Grids of 608 PUs each
Facts about "Colossus - Graphcore"
codename | Colossus + |
designer | Graphcore + |
first launched | 2018 + |
full page name | graphcore/microarchitectures/colossus + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | Colossus + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |