From WikiChip
Difference between revisions of "intel/cores/cascade lake ap"
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+ | == Overview == | ||
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+ | === Common Features === | ||
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+ | {{clear}} | ||
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+ | == Cascade Lake AP Processors == | ||
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== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Revision as of 13:52, 10 June 2018
Edit Values | |
Cascade Lake AP | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Microarchitecture | |
ISA | x86-64 |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Technology | CMOS |
Packaging | |
Unknown package "intel,bga_5903" |
Cascade Lake AP is a planned series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform.
Overview
This section is empty; you can help add the missing info by editing this page. |
Common Features
This section is empty; you can help add the missing info by editing this page. |
Cascade Lake AP Processors
This section is empty; you can help add the missing info by editing this page. |
See also
|
Facts about "Cascade Lake AP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake AP + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |