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'''Exynos 9610''' is a {{arch|64}} [[ARM]] mid-range microprocessor designed by [[Samsung]] set to launch in late [[2018]]. Manufactured on Samsung's [[10 nm process]], the 9610 features eight cores consisting of four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.3 GHz and four {{armh|Cortex-A53|l=arch}} [[little cores]] operating at up to 1.6 GHz. This processor incorporates a {{armh|Mali-G72}} MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as [[802.11ac]], [[Bluetooth]] 5.0, and a 24 [[megapixel|MP]] [[image signal processor|ISP]].
 
'''Exynos 9610''' is a {{arch|64}} [[ARM]] mid-range microprocessor designed by [[Samsung]] set to launch in late [[2018]]. Manufactured on Samsung's [[10 nm process]], the 9610 features eight cores consisting of four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.3 GHz and four {{armh|Cortex-A53|l=arch}} [[little cores]] operating at up to 1.6 GHz. This processor incorporates a {{armh|Mali-G72}} MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as [[802.11ac]], [[Bluetooth]] 5.0, and a 24 [[megapixel|MP]] [[image signal processor|ISP]].
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{{unknown features}}
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== Cache ==
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{{main|arm_holdings/microarchitectures/cortex-a73#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A73 § Cache||l2=Cortex-A55 § Cache}}
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For the {{armh|Cortex-A73|l=arch}} core cluster:
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{{cache size}}
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For the {{armh|Cortex-A55|l=arch}} cluster:
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{{cache size}}
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== Memory controller ==
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{{memory controller
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|type=LPDDR4X-3200
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|ecc=No
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|max mem=6 GiB
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|controllers=4
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|channels=4
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|width=16 bit
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|frequency=1800 MHz
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|bandwidth schan=2.98 GiB/s
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|bandwidth dchan=5.96 GiB/s
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|bandwidth qchan=11.92 GiB/s
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}}
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== Graphics ==
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{{integrated graphics
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| gpu                = Mali-G72
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| device id          =
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| designer            = ARM Holdings
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| execution units    = 3
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| max displays        = 2
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| max memory          =
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| frequency          = ? MHz
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| max frequency      =
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| output crt          =
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| output sdvo        =
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| output dsi          = Yes
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| output edp          =
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| output dp          =
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| output hdmi        =
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| output vga          =
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| output dvi          =
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| directx ver        = 12
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| opengl ver        =
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| opengl es ver      = 3.2
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| openvg ver        = 1.1
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| opencl ver        = 2
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| vulkan ver        = 1.0
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| hdmi ver          =
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| dp ver            =
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| edp ver            =
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| max res hdmi      =
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| max res hdmi freq  =
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| max res dp        =
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| max res dp freq    =
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| max res edp        =
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| max res edp freq  =
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| max res vga        =
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| max res vga freq  =
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}}
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== Wireless ==
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{{wireless links
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| 2g                =
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| csd              =
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| gsm              =
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| gprs              =
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| edge              =
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| cdmaone          =
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| is-95a            =
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| is-95b            =
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| 3g                =
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| cdma2000          =
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| cdma2000 1x      =
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| cdma2000 1xev-do  =
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| cdma2000 1x adv  =
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| umts              =
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| wcdma            = 
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| td-scdma          =
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| dc-hsdpa          =
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| hsdpa            =
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| hsupa            =
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| 4g                = Yes
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| lte a            = Yes
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| e-utran          =
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| ue cat dl        = 12
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| ue cat dl rate    = 600 Mbps
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| ue cat ul        = 13
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| ue cat ul rate    = 150 Mbps
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}}
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== ISP ==
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* 24MP Rear
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* 24MP Front
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* 16MP+16MP Dual
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|trustzone=No
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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|pmuv3=No
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|crc32=Yes
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|crypto=Yes
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|fp=Yes
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|fp16=No
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|profile=No
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|ras=No
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|simd=No
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|rdm=No
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}}
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== Utilizing devices ==
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<!--
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* [[used by::XXXXXXXXX]]
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-->
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{{expand list}}

Revision as of 23:40, 29 March 2018

Edit Values
Exynos 9610
Exynos79610.png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9610
MarketMobile
IntroductionMarch 22, 2018 (announced)
October, 2018 (launched)
General Specs
FamilyExynos
SeriesExynos 7
Frequency2,300 MHz, 1,600 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A73, Cortex-A53
Core NameCortex-A73, Cortex-A53
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)

Exynos 9610 is a 64-bit ARM mid-range microprocessor designed by Samsung set to launch in late 2018. Manufactured on Samsung's 10 nm process, the 9610 features eight cores consisting of four Cortex-A73 big cores operating at up to 2.3 GHz and four Cortex-A53 little cores operating at up to 1.6 GHz. This processor incorporates a Mali-G72 MP3 GPU and supports up to 4 GiB of quad-channel LPDDR4x-3200 memory. This chip incorporates an LTE modem supporting Cat 12 600Mbps download and Cat 13 150Mbps upload as well as 802.11ac, Bluetooth 5.0, and a 24 MP ISP.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main articles: Cortex-A73 § Cache and Cortex-A55 § Cache


For the Cortex-A73 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3200
Supports ECCNo
Max Mem6 GiB
Frequency1800 MHz
Controllers4
Channels4
Width16 bit
Bandwidth
Single 2.98 GiB/s
Double 5.96 GiB/s
Quad 11.92 GiB/s


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G72
DesignerARM Holdings
Execution Units3Max Displays2
Frequency? MHz
"? MHz" is not a number.
OutputDSI
Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL12 (600 Mbps)
UE Cat UL13 (150 Mbps)

ISP

  • 24MP Rear
  • 24MP Front
  • 16MP+16MP Dual

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/9610&oldid=75694"
Facts about "Exynos 9610 - Samsung"
RDF feed
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) + and 1,600 MHz (1.6 GHz, 1,600,000 kHz) +
core count8 +
core nameCortex-A73 + and Cortex-A53 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedMarch 22, 2018 +
first launchedOctober 2018 +
full page namesamsung/exynos/9610 +
has 4g supporttrue +
has ecc memory supportfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G72 +
integrated gpu designerARM Holdings +
integrated gpu execution units3 +
isaARMv8 +
isa familyARM +
ldate3000 +
main imageFile:Exynos79610.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory channels4 +
microarchitectureCortex-A73 + and Cortex-A53 +
model number9610 +
nameExynos 9610 +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesExynos 7 +
smp max ways1 +
supported memory typeLPDDR4X-3200 +
technologyCMOS +
thread count8 +
user equipment category downlink12 +
user equipment category uplink13 +
word size64 bit (8 octets, 16 nibbles) +