From WikiChip
Difference between revisions of "amd/ryzen 5/2600x"
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+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen+#Memory_Hierarchy|l1=Zen+ § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=576 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=6x64 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=6x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=3 MiB | ||
+ | |l2 break=6x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=16 MiB | ||
+ | |l3 break=2x8 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | }} |
Revision as of 06:45, 7 March 2018
Edit Values | |
Ryzen 5 2600X | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 2600X |
Market | Desktop |
Introduction | March, 2018 (announced) April 19, 2018 (launched) |
Release Price | $249 |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | 2000 |
Locked | No |
Frequency | 3,600 MHz |
Turbo Frequency | 4,250 MHz (1 core) |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 36 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen+ |
Chipset | Promontory |
Core Name | Pinnacle Ridge |
Process | 12 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 95 W |
Packaging | |
Template:packages/amd/socket am4 |
Ryzen 5 2600X is a 64-bit hexa-core mid-range performance x86 desktop microprocessor set to be introduced by AMD in early 2018. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 2600X operates at a base frequency of 3.6 GHz with a TDP of 95 W and a Boost frequency of up to 4.25 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2933 memory.
Cache
- Main article: Zen+ § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Ryzen 5 2600X - AMD"
base frequency | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
chipset | Promontory + |
clock multiplier | 36 + |
core count | 6 + |
core name | Pinnacle Ridge + |
designer | AMD + |
family | Ryzen 5 + |
first announced | March 2018 + |
first launched | April 19, 2018 + |
full page name | amd/ryzen 5/2600x + |
has locked clock multiplier | false + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | 3000 + |
manufacturer | GlobalFoundries + |
market segment | Desktop + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
microarchitecture | Zen+ + |
model number | 2600X + |
name | Ryzen 5 2600X + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
release price | $ 249.00 (€ 224.10, £ 201.69, ¥ 25,729.17) + |
series | 2000 + |
smp max ways | 1 + |
tdp | 95 W (95,000 mW, 0.127 hp, 0.095 kW) + |
technology | CMOS + |
thread count | 12 + |
turbo frequency (1 core) | 4,250 MHz (4.25 GHz, 4,250,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |