From WikiChip
Difference between revisions of "intel/xeon d/d-2141i"
| Line 65: | Line 65: | ||
|bandwidth dchan=39.74 GiB/s | |bandwidth dchan=39.74 GiB/s | ||
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions main | ||
| + | | | ||
| + | {{expansions entry | ||
| + | |type=PCIe | ||
| + | |pcie revision=3.0 | ||
| + | |pcie lanes=48 | ||
| + | |pcie config=x16 | ||
| + | |pcie config 2=x8 | ||
| + | |pcie config 3=x4 | ||
| + | }} | ||
| + | }} | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | |real=Yes | ||
| + | |protected=Yes | ||
| + | |smm=Yes | ||
| + | |fpu=Yes | ||
| + | |x8616=Yes | ||
| + | |x8632=Yes | ||
| + | |x8664=Yes | ||
| + | |nx=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=Yes | ||
| + | |sse3=Yes | ||
| + | |ssse3=Yes | ||
| + | |sse41=Yes | ||
| + | |sse42=Yes | ||
| + | |sse4a=No | ||
| + | |avx=Yes | ||
| + | |avx2=Yes | ||
| + | |avx512f=Yes | ||
| + | |avx512cd=Yes | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=Yes | ||
| + | |avx512dq=Yes | ||
| + | |avx512vl=Yes | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| + | |avx512units=2 | ||
| + | |abm=Yes | ||
| + | |tbm=No | ||
| + | |bmi1=Yes | ||
| + | |bmi2=Yes | ||
| + | |fma3=Yes | ||
| + | |fma4=No | ||
| + | |aes=Yes | ||
| + | |rdrand=Yes | ||
| + | |sha=No | ||
| + | |xop=No | ||
| + | |adx=Yes | ||
| + | |clmul=Yes | ||
| + | |f16c=Yes | ||
| + | |tbt1=No | ||
| + | |tbt2=Yes | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=Yes | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |ivmd=Yes | ||
| + | |intelnodecontroller=No | ||
| + | |intelnode=No | ||
| + | |kpt=No | ||
| + | |ptt=No | ||
| + | |intelrunsure=No | ||
| + | |mbe=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=Yes | ||
| + | |tsx=Yes | ||
| + | |txt=Yes | ||
| + | |ht=Yes | ||
| + | |vpro=Yes | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=Yes | ||
| + | |sgx=No | ||
| + | |securekey=Yes | ||
| + | |osguard=Yes | ||
| + | |intqat=No | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
}} | }} | ||
Revision as of 22:22, 1 February 2018
| Edit Values | |
| Xeon D-2141I | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | D-2141I |
| Market | Server, Embedded |
| Release Price | $555 |
| Shop | Amazon |
| General Specs | |
| Family | Xeon D |
| Series | D-2000 |
| Locked | Yes |
| Frequency | 2,200 MHz |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Skylake (server) |
| Core Name | Skylake-D |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 16 |
| Max Memory | 512 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| TDP | 65 W |
Xeon D-2141I is a 64-bit octa-core high-performance x86 microserver processor set to be introduced by Intel in early 2018. Fabricated on Intel's 14nm+ process based on the Skylake microarchitecture, this chip operates at 2.2 GHz with a TDP of 65 W.
Contents
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "Xeon D-2141I - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-2141I - Intel#pcie + |
| base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
| core count | 8 + |
| core name | Skylake-D + |
| designer | Intel + |
| family | Xeon D + |
| full page name | intel/xeon d/d-2141i + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel identity protection technology support | true + |
| has intel secure key technology | true + |
| has intel speed shift technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
| ldate | 3000 + |
| manufacturer | Intel + |
| market segment | Server + and Embedded + |
| max cpu count | 1 + |
| max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
| max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
| max memory channels | 4 + |
| microarchitecture | Skylake (server) + |
| model number | D-2141I + |
| name | Xeon D-2141I + |
| number of avx-512 execution units | 2 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 555.00 (€ 499.50, £ 449.55, ¥ 57,348.15) + |
| series | D-2000 + |
| smp max ways | 1 + |
| supported memory type | DDR4-2666 + |
| tdp | 65 W (65,000 mW, 0.0872 hp, 0.065 kW) + |
| technology | CMOS + |
| thread count | 16 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
| x86/has memory protection extensions | true + |