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Difference between revisions of "vti/vl86cx/vy86c810"
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− | '''VY86C810''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1996]]. This processor is based on the {{armh| | + | '''VY86C810''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1996]]. This processor is based on the {{armh|ARM8|l=arch}} microarchitecture ({{armh|ARM810|l=core}} core) and is manufactured on [[VLSI Technology|VLSI]]'s [[0.5 µm process]] and operating at 50 MHz. |
== Cache == | == Cache == | ||
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|l1 policy=write-through | |l1 policy=write-through | ||
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+ | == Documents == | ||
+ | * [[:File:vlsi arm810-710.pdf|VY86C710A/VY86C710A2/VY86C810 Product Brief]] |
Latest revision as of 16:32, 13 December 2017
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VY86C810 | |||||||||
General Info | |||||||||
Designer | ARM Holdings | ||||||||
Manufacturer | VLSI Technology | ||||||||
Model Number | VY86C810 | ||||||||
Part Number | VY86C810 | ||||||||
Market | Embedded, Desktop | ||||||||
Introduction | August 26, 1996 (announced) November, 1996 (launched) | ||||||||
General Specs | |||||||||
Family | VL86Cx | ||||||||
Frequency | 50 MHz | ||||||||
Microarchitecture | |||||||||
ISA | ARMv4 (ARM) | ||||||||
Microarchitecture | ARM8 | ||||||||
Core Name | ARM810 | ||||||||
Process | 0.5 µm | ||||||||
Technology | CMOS | ||||||||
Die | 53.5 mm² | ||||||||
Word Size | 32 bit | ||||||||
Cores | 1 | ||||||||
Threads | 1 | ||||||||
Max Memory | 4 GiB | ||||||||
Max Address Mem | 0xFFFFFFFF | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Power dissipation | 500 mW | ||||||||
Vcore | 3.3 V ± 10 % | ||||||||
Tstorage | -65 °C – -150 °C | ||||||||
Tambient | -10 °C – 70 °C | ||||||||
Packaging | |||||||||
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VY86C810 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1996. This processor is based on the ARM8 microarchitecture (ARM810 core) and is manufactured on VLSI's 0.5 µm process and operating at 50 MHz.
Cache[edit]
- Main article: ARM8 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Documents[edit]
Facts about "VY86C810 - VTI"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | VY86C810 - VTI#package + |
base frequency | 50 MHz (0.05 GHz, 50,000 kHz) + |
core count | 1 + |
core name | ARM810 + |
core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
core voltage tolerance | 10 % + |
designer | ARM Holdings + |
die area | 53.5 mm² (0.0829 in², 0.535 cm², 53,500,000 µm²) + |
family | VL86Cx + |
first announced | August 26, 1996 + |
first launched | November 1996 + |
full page name | vti/vl86cx/vy86c810 + |
instance of | microprocessor + |
isa | ARMv4 + |
isa family | ARM + |
l1$ description | 64-way set associative + |
l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
ldate | November 1996 + |
manufacturer | VLSI Technology + |
market segment | Embedded + and Desktop + |
max ambient temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory address | 0xFFFFFFFF + |
max storage temperature | 123.15 K (-150 °C, -238 °F, 221.67 °R) + |
microarchitecture | ARM8 + |
min ambient temperature | 263.15 K (-10 °C, 14 °F, 473.67 °R) + |
min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
model number | VY86C810 + |
name | VY86C810 + |
package | TQFP-144 + |
part number | VY86C810 + |
power dissipation | 0.5 W (500 mW, 6.705e-4 hp, 5.0e-4 kW) + |
process | 500 nm (0.5 μm, 5.0e-4 mm) + |
smp max ways | 1 + |
technology | CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |