Latest revision as of 15:14, 13 December 2017

Edit Values
Atom N280
Atom N280
General Info
Designer	Intel
Manufacturer	Intel
Model Number	N280
Part Number	AU80586GF028D
S-Spec	SLGL9
Market	Mobile
Introduction	2008 (announced) February 7, 2009 (launched)
Shop	Amazon
General Specs
Family	Atom
Series	N200
Locked	Yes
Frequency	1,666.66 MHz
Bus type	FSB
Bus speed	166.66 MHz
Bus rate	666.66 MT/s
Clock multiplier	10
CPUID	106C2
Microarchitecture
ISA	x86-32 (x86)
Microarchitecture	Bonnell
Platform	Nettop 2008
Chipset	Calistoga
Core Name	Diamondville
Core Family	6
Core Model	112
Core Stepping	C0
Process	45 nm
Transistors	47,212,207
Technology	CMOS
Die	25.9638 mm² 7.94 mm × 3.27 mm
Word Size	64 bit
Cores	1
Threads	2
Max Memory	8 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	0.9 V-1.1625 V
VI/O	1.1 V ± 0.05 V
TDP	2.5 W
Tjunction	0 °C – 90 °C
Tcase	0 °C – 85.2 °C
Tstorage	-40 °C – 85 °C
Packaging
Package FCBGA-437 (FCBGA) Dimension 22 mm x 22 mm x 1.6 mm Pin Count 437 Socket BGA-437 (BGA)

Atom N280 is an ultra-low power 32-bit x86 single-core microprocessor introduced by Intel in early 2009. The N280 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's 45 nm process, was based on the Bonnell microarchitecture. The Atom N280 operates at 1.66 GHz with a TDP of 2.5 W. The MPU features a legacy 667 MT/s front-side bus. This specific model has a faster bus speed vs all other Diamondville models (operating at 166.66 MHz).

Cache[edit]

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 56 KiB 57,344 B 0.0547 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L1D$ 24 KiB 24,576 B 0.0234 MiB 1x24 KiB 6-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 8-way set associative

Memory controller[edit]

This processor has no integrated memory controller.

Graphics[edit]

This processor has no integrated graphics.

Features[edit]

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading EIST Enhanced SpeedStep Technology