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{{freescale title|QorIQ P1012}}
 
{{freescale title|QorIQ P1012}}
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{{mpu}}
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{{chip
 +
|name=QorIQ P1012
 +
|image=qoriq p1012.png
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|designer=Freescale
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|manufacturer=IBM
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|model number=P1012
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|market=Networking
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|market 2=Embedded
 +
|first announced=December 7, 2009
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|first launched=January, 2010
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|family=QorIQ
 +
|series=P1
 +
|frequency=533
 +
|frequency 2=800
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|isa=Power ISA v2.03
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|isa family=Power
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|microarch=e500
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|core name=e500 v2
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|process=45 nm
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|technology=CMOS
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|word size=32 bit
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|core count=1
 +
|thread count=1
 +
|power=1.6 W
 +
|package module 1={{packages/freescale/te-pbga-ii-689}}
 +
}}
 +
'''QorIQ P1012''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in late [[2009]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 533 MHz (with higher frequencies offered later on) and supports 32-bit DDR3-800 memory.
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== Cache ==
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{{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}}
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{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
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|l1d cache=32 KiB
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|l1d break=1x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=
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|l2 cache=256 KiB
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|l2 break=1x256 KiB
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|l2 desc=8-way set associative
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|l2 policy=Write-through
 +
}}
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== Memory controller ==
 +
{{memory controller
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|type=DDR3-800
 +
|ecc=Yes
 +
|controllers=1
 +
|channels=1
 +
|width=32 bit
 +
|max bandwidth=2.98 GiB/s
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|bandwidth schan=2.98 GiB/s
 +
}}
 +
 
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== Expansions ==
 +
* 3x 10/100/1000 Eithernet with 2x SGMII
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* 2x PCIe 1.0a controllers with 4 SerDes
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* 2x USB 2.0
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* SD/MMC
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* SPI
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* 2x I2C
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* UART
 +
* SEC 3.3 Security Acceleration
 +
 
 +
== Block Diagram ==
 +
: [[File:qoriq p1012 block diagram.png|800px]]
 +
 
 +
== Documents ==
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* [[:File:p1012-p1021.pdf|P1012/P1021 Product Brief]]

Latest revision as of 15:13, 13 December 2017

Edit Values
QorIQ P1012
qoriq p1012.png
General Info
DesignerFreescale
ManufacturerIBM
Model NumberP1012
MarketNetworking, Embedded
IntroductionDecember 7, 2009 (announced)
January, 2010 (launched)
General Specs
FamilyQorIQ
SeriesP1
Frequency533, 800
Microarchitecture
ISAPower ISA v2.03 (Power)
Microarchitecturee500
Core Namee500 v2
Process45 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Electrical
Power dissipation1.6 W
Packaging
PackageTE-PBGA-II-689 (TE PBGA-II)
Temperature-Enhanced Plastic BGA
Dimension31 mm x 31 mm
Contacts689

QorIQ P1012 is a 32-bit embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 533 MHz (with higher frequencies offered later on) and supports 32-bit DDR3-800 memory.

Cache[edit]

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associativeWrite-through

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s

Expansions[edit]

  • 3x 10/100/1000 Eithernet with 2x SGMII
  • 2x PCIe 1.0a controllers with 4 SerDes
  • 2x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.3 Security Acceleration

Block Diagram[edit]

qoriq p1012 block diagram.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p1012&oldid=70339"
Facts about "QorIQ P1012 - Freescale"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
QorIQ P1012 - Freescale#package +
base frequency533 MHz (0.533 GHz, 533,000 kHz) + and 800 MHz (0.8 GHz, 800,000 kHz) +
core count1 +
core namee500 v2 +
designerFreescale +
familyQorIQ +
first announcedDecember 7, 2009 +
first launchedJanuary 2010 +
full page namefreescale/qoriq/p1012 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaPower ISA v2.03 +
isa familyPower +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateJanuary 2010 +
main imageFile:qoriq p1012.png +
manufacturerIBM +
market segmentNetworking + and Embedded +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
microarchitecturee500 +
model numberP1012 +
nameQorIQ P1012 +
packageTE-PBGA-II-689 +
power dissipation1.6 W (1,600 mW, 0.00215 hp, 0.0016 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
seriesP1 +
supported memory typeDDR3-800 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +