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Difference between revisions of "cavium/octeon plus/cn5860-1000bg1521-scp"
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m (Bot: moving all {{mpu}} to {{chip}})
 
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{{cavium title|CN5860-1000 SCP}}
 
{{cavium title|CN5860-1000 SCP}}
{{mpu
+
{{chip
 
| name                = Cavium CN5860-1000 SCP
 
| name                = Cavium CN5860-1000 SCP
 
| no image            =  
 
| no image            =  
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| model number        = CN5860-1000 SCP
 
| model number        = CN5860-1000 SCP
 
| part number        = CN5860-1000BG1521-SCP
 
| part number        = CN5860-1000BG1521-SCP
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Network
 
| market              = Network
 
| first announced    = October 9, 2006
 
| first announced    = October 9, 2006
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| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
| release price      =  
+
| release price      = $987
  
 
| family              = OCTEON Plus
 
| family              = OCTEON Plus
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| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  
| process            = 130 nm
+
| process            = 90 nm
 
| transistors        =  
 
| transistors        =  
 
| technology          = CMOS
 
| technology          = CMOS
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| max memory addr    =  
 
| max memory addr    =  
  
| electrical          = Yes
+
 
 
| power              = 40 W
 
| power              = 40 W
 
| v core              =  
 
| v core              =  
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| tambient max        =  
 
| tambient max        =  
  
| packaging          = Yes
+
|package module 1={{packages/cavium/fcbga-1521}}
| package 0          = FCBGA-1521
 
| package 0 type      = FCBGA
 
| package 0 pins      = 1521
 
| package 0 pitch    =  
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0            = BGA-1521
 
| socket 0 type      = BGA
 
 
}}
 
}}
 +
'''CN5860-1000 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
  
  
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|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-800
 +
|ecc=Yes
 +
|max mem=
 +
|controllers=1
 +
|channels=1
 +
|width=128 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|pcix width=64 bit
 +
|pcix clock=133.33 MHz
 +
|pcix rate=1,017.25 MiB/s
 +
|pcix extra=host or slave
 +
|uart=yes
 +
|uart ports=2
 +
|gp io=Yes
 +
}}
 +
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=8
 +
|spi opts=Yes
 +
|spi42=Yes
 +
|spi42 ports=2
 +
}}
 +
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|encryption=Yes
 +
|encryption type=DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI
 +
|tcp=Yes
 +
|qos=Yes
 +
}}
 +
 +
== Block diagram ==
 +
[[File:octeon plus cn58xx.png|750px]]
 +
 +
== Datasheet ==
 +
* [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]]

Latest revision as of 15:13, 13 December 2017

Edit Values
Cavium CN5860-1000 SCP
octeon plus chip.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5860-1000 SCP
Part NumberCN5860-1000BG1521-SCP
MarketNetwork
IntroductionOctober 9, 2006 (announced)
February, 2007 (launched)
Release Price$987
General Specs
FamilyOCTEON Plus
SeriesCN58xx
Frequency1,000 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads16
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation40 W
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

CN5860-1000 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.


Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB64-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
16x16 KiB64-way set associative 

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2

GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI
Networking
TCPYes
QoSYes

Block diagram[edit]

octeon plus cn58xx.png

Datasheet[edit]

l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description64-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description64-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +