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Difference between revisions of "cavium/octeon plus/cn5860-1000bg1521-scp"
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{{cavium title|CN5860-1000 SCP}} | {{cavium title|CN5860-1000 SCP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN5860-1000 SCP | | name = Cavium CN5860-1000 SCP | ||
| no image = | | no image = | ||
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| model number = CN5860-1000 SCP | | model number = CN5860-1000 SCP | ||
| part number = CN5860-1000BG1521-SCP | | part number = CN5860-1000BG1521-SCP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
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| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = | + | | release price = $987 |
| family = OCTEON Plus | | family = OCTEON Plus | ||
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| core model = | | core model = | ||
| core stepping = | | core stepping = | ||
− | | process = | + | | process = 90 nm |
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS | ||
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| max memory addr = | | max memory addr = | ||
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| power = 40 W | | power = 40 W | ||
| v core = | | v core = | ||
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| tambient max = | | tambient max = | ||
− | + | |package module 1={{packages/cavium/fcbga-1521}} | |
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− | | package | ||
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}} | }} | ||
+ | '''CN5860-1000 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration. | ||
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|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
}} | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=128 bit | ||
+ | |max bandwidth=11.92 GiB/s | ||
+ | |bandwidth schan=11.92 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=64 bit | ||
+ | |pcix clock=133.33 MHz | ||
+ | |pcix rate=1,017.25 MiB/s | ||
+ | |pcix extra=host or slave | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=8 | ||
+ | |spi opts=Yes | ||
+ | |spi42=Yes | ||
+ | |spi42 ports=2 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:octeon plus cn58xx.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]] |
Latest revision as of 15:13, 13 December 2017
Edit Values | |||||||
Cavium CN5860-1000 SCP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN5860-1000 SCP | ||||||
Part Number | CN5860-1000BG1521-SCP | ||||||
Market | Network | ||||||
Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
Release Price | $987 | ||||||
General Specs | |||||||
Family | OCTEON Plus | ||||||
Series | CN58xx | ||||||
Frequency | 1,000 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Process | 90 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
Power dissipation | 40 W | ||||||
Packaging | |||||||
|
CN5860-1000 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Networking[edit]
Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5860-1000 SCP - Cavium"
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |