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Difference between revisions of "cavium/octeon plus/cn5734-1000bg1217-ssp"
< cavium‎ | octeon plus

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{{cavium title|CN5734-1000 SSP}}
 
{{cavium title|CN5734-1000 SSP}}
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{{mpu
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{{chip
 
| name                = Cavium CN5734-1000 SSP
 
| name                = Cavium CN5734-1000 SSP
 
| no image            =  
 
| no image            =  
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| model number        = CN5734-1000 SSP
 
| model number        = CN5734-1000 SSP
 
| part number        = CN5734-1000BG1217-SSP
 
| part number        = CN5734-1000BG1217-SSP
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| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Storage
 
| market              = Storage
 
| first announced    = Jun 26, 2007
 
| first announced    = Jun 26, 2007
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| tambient max        =  
 
| tambient max        =  
  
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| packaging          = Yes
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|package module 1={{packages/cavium/fcbga-1217}}
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| package 0          = FCBGA-1217
 
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| package 0 type      = FCBGA
 
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| package 0 pins      = 1217
 
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| package 0 pitch    =  
 
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| package 0 width    =
 
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| package 0 length    =
 
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| package 0 height    =
 
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| socket 0            = BGA-1217
 
−
| socket 0 type      = BGA
 
 
}}
 
}}
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'''CN5734-1000 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.
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== Cache ==
 +
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 +
{{cache size
 +
|l1 cache=288 KiB
 +
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 +
|l1d cache=96 KiB
 +
|l1d break=6x16 KiB
 +
|l2 cache=1 MiB
 +
|l2 break=1x1 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-800
 +
|ecc=Yes
 +
|max mem=
 +
|controllers=1
 +
|channels=2
 +
|width=64 bit
 +
|max bandwidth=11.92 GiB/s
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|bandwidth schan=5.96 GiB/s
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|bandwidth dchan=11.92 GiB/s
 +
}}
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 +
== Expansions ==
 +
{{expansions
 +
|pcie revision=1.0
 +
|pcie lanes=8
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|pcie config=x4
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|pcie config 2=x8
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|uart=yes
 +
|gp io=Yes
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}}
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 +
== Networking ==
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Interface options:
 +
* 8-lanes [[PCIe]] + 8-lanes PCIe
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* 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
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* 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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{{network
 +
|mii opts=Yes
 +
|sgmii=yes
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|sgmii ports=4
 +
|xaui=1
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|xaui ports=1
 +
}}
 +
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|encryption=Yes
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|encryption type=3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
 +
|compression=Yes
 +
|decompression=Yes
 +
|tcp=Yes
 +
|qos=Yes
 +
|raid=Yes
 +
|raid5=Yes
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|raid6=Yes
 +
}}
 +
 +
== Block diagram ==
 +
[[File:cn57xx block diagram.png|750px]]
 +
 +
== Datasheet ==
 +
* [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]]

Latest revision as of 15:12, 13 December 2017

Edit Values
Cavium CN5734-1000 SSP
Octeon CN57xx.svg
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5734-1000 SSP
Part NumberCN5734-1000BG1217-SSP
MarketStorage
IntroductionJun 26, 2007 (announced)
August, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN57xx
Frequency1,000 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores6
Threads6
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1217 (BGA)
Dimension40 mm x 40 mm
Ball Count1217
InterconnectBGA-1217

CN5734-1000 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$288 KiB
294,912 B
0.281 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB  
L1D$96 KiB
98,304 B
0.0938 MiB
6x16 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART
GP I/OYes


Networking[edit]

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
Types3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram[edit]

cn57xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5734-1000bg1217-ssp&oldid=70252"
Facts about "CN5734-1000 SSP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5734-1000 SSP - Cavium#package + and CN5734-1000 SSP - Cavium#io +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count6 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5734-1000bg1217-ssp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size288 KiB (294,912 B, 0.281 MiB) +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5734-1000 SSP +
nameCavium CN5734-1000 SSP +
packageFCBGA-1217 +
part numberCN5734-1000BG1217-SSP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count6 +
word size64 bit (8 octets, 16 nibbles) +