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Difference between revisions of "amd/cores/rome"
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[[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | [[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | ||
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+ | == See also == | ||
+ | {{amd zen 2 core see also}} |
Revision as of 00:15, 10 December 2017
Edit Values | |
Rome | |
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General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Introduction | May 16, 2017 (announced) |
Microarchitecture | |
ISA | x86-64 |
Microarchitecture | Zen 2 |
Word Size | 8 octets 64 bit16 nibbles |
Process | 7 nm 0.007 μm 7.0e-6 mm |
Technology | CMOS |
Succession | |
Rome is the codename for AMD's high-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture serving as a successor to Naples. Rome-based chips are set to be fabricated on GlobalFoundries' 7 nm process.
See also
|
Facts about "Rome - Cores - AMD"
designer | AMD + |
first announced | May 16, 2017 + |
instance of | core + |
isa | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen 2 + |
name | Rome + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |