From WikiChip
Difference between revisions of "intel/xeon w/w-2145"
Line 37: | Line 37: | ||
|max memory=512 GiB | |max memory=512 GiB | ||
|tdp=140 W | |tdp=140 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=70 °C | ||
|package module 1={{packages/intel/fclga-2066}} | |package module 1={{packages/intel/fclga-2066}} | ||
}} | }} |
Revision as of 02:59, 6 September 2017
Template:mpu W-2145 is a 64-bit octa-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.7 GHz with a TDP of 140 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
Contents
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||||
|
Expansions
Expansion Options |
|||||
|
Features
[Edit/Modify Supported Features]
Facts about "Xeon W-2145 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-2145 - Intel#pcie + |
base frequency | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 37 + |
core count | 8 + |
core family | 6 + |
core name | Skylake W + |
core stepping | U0 + |
designer | Intel + |
family | Xeon W + |
first announced | August 29, 2017 + |
first launched | August 29, 2017 + |
full page name | intel/xeon w/w-2145 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | August 29, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Workstation + |
max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | W-2145 + |
name | Xeon W-2145 + |
number of avx-512 execution units | 2 + |
package | FCLGA-2066 + |
part number | CD8067303533601 + |
platform | Basin Falls + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,113.00 (€ 1,001.70, £ 901.53, ¥ 115,006.29) + |
release price (tray) | $ 1,113.00 (€ 1,001.70, £ 901.53, ¥ 115,006.29) + |
s-spec | SR3LQ + |
series | W-2000 + |
smp max ways | 1 + |
socket | Socket R4 + |
supported memory type | DDR4-2666 + |
tdp | 140 W (140,000 mW, 0.188 hp, 0.14 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
turbo frequency (2 cores) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
turbo frequency (3 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (4 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (5 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (6 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (7 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (8 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |