Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/goldmont plus"
(remove the cache for now) |
(https://twitter.com/FanlessTech/status/867867363022184449 "Exclusive: Gemini Lake features Goldmont Plus core, 4MB cache (up from 2MB), DDR4, integrated WiFi / BT") |
||
| Line 28: | Line 28: | ||
|extension 12=RDRND | |extension 12=RDRND | ||
|extension 13=SHA | |extension 13=SHA | ||
| + | |l1i=32 KiB | ||
| + | |l1i per=Core | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1d=24 KiB | ||
| + | |l1d per=Core | ||
| + | |l1d desc=6-way set associative | ||
| + | |l2=2 MiB | ||
| + | |l2 per=2 Cores | ||
| + | |l2 desc=16-way set associative | ||
|core name=Gemini Lake | |core name=Gemini Lake | ||
|predecessor=Goldmont | |predecessor=Goldmont | ||
| Line 45: | Line 54: | ||
=== Key changes from {{\\|Goldmont}} === | === Key changes from {{\\|Goldmont}} === | ||
* 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref> | * 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref> | ||
| − | + | * Integrated Intel wireless controller ([[IEEE 802.11ac]]) | |
=== Block Diagram === | === Block Diagram === | ||
{{empty section}} | {{empty section}} | ||
Revision as of 07:24, 26 July 2017
| Edit Values | |
| Goldmont Plus µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 14 nm |
| Core Configs | 2, 4 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-16, x86-32, x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cache | |
| L1I Cache | 32 KiB/Core 8-way set associative |
| L1D Cache | 24 KiB/Core 6-way set associative |
| L2 Cache | 2 MiB/2 Cores 16-way set associative |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Goldmont Plus is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.
Codenames
| Platform | Core | Target |
|---|---|---|
| Gemini Lake | Gemini Lake | Tablets, Entry-level PCs |
Architecture
Key changes from Goldmont
- 4-way decode (from 3-way)[1]
- Integrated Intel wireless controller (IEEE 802.11ac)
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Core
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Goldmont Plus - Microarchitectures - Intel"
| codename | Goldmont Plus + |
| core count | 2 + and 4 + |
| designer | Intel + |
| full page name | intel/microarchitectures/goldmont plus + |
| instance of | microarchitecture + |
| instruction set architecture | x86-16 +, x86-32 + and x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Goldmont Plus + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |