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Difference between revisions of "intel/microarchitectures/goldmont plus"
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Revision as of 05:01, 26 July 2017
| Edit Values | |
| Goldmont Plus µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Process | 14 nm |
| Core Configs | 2, 4 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-16, x86-32, x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Goldmont Plus is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.
Codenames
| Platform | Core | Target |
|---|---|---|
| Gemini Lake | Gemini Lake | Tablets, Entry-level PCs |
Architecture
Key changes from Goldmont
- 4-way decode (from 3-way)[1]
Block Diagram
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This section is empty; you can help add the missing info by editing this page. |
Core
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This section is empty; you can help add the missing info by editing this page. |
Facts about "Goldmont Plus - Microarchitectures - Intel"
| codename | Goldmont Plus + |
| core count | 2 + and 4 + |
| designer | Intel + |
| full page name | intel/microarchitectures/goldmont plus + |
| instance of | microarchitecture + |
| instruction set architecture | x86-16 +, x86-32 + and x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Goldmont Plus + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
