From WikiChip
					
    Difference between revisions of "intel/xeon platinum/8160f"    
                	
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| |l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
| |l3 policy=write-back | |l3 policy=write-back | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=DDR4-2666 | ||
| + | |ecc=Yes | ||
| + | |max mem=768 GiB | ||
| + | |controllers=2 | ||
| + | |channels=6 | ||
| + | |max bandwidth=119.21 GiB/s | ||
| + | |bandwidth schan=19.87 GiB/s | ||
| + | |bandwidth dchan=39.74 GiB/s | ||
| + | |bandwidth qchan=79.47 GiB/s | ||
| + | |bandwidth hchan=119.21 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision      = 3.0 | ||
| + | | pcie lanes         = 48 | ||
| + | | pcie config        = x16 | ||
| + | | pcie config 2      = x8 | ||
| + | | pcie config 3      = x4 | ||
| + | }} | ||
| + | |||
| + | == Features ==  | ||
| + | {{x86 features | ||
| + | |real=Yes | ||
| + | |protected=Yes | ||
| + | |smm=Yes | ||
| + | |fpu=Yes | ||
| + | |x8616=Yes | ||
| + | |x8632=Yes | ||
| + | |x8664=Yes | ||
| + | |nx=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=Yes | ||
| + | |sse3=Yes | ||
| + | |ssse3=Yes | ||
| + | |sse41=Yes | ||
| + | |sse42=Yes | ||
| + | |sse4a=No | ||
| + | |avx=Yes | ||
| + | |avx2=Yes | ||
| + | |avx512f=Yes | ||
| + | |avx512cd=Yes | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=Yes | ||
| + | |avx512dq=Yes | ||
| + | |avx512vl=Yes | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| + | |abm=Yes | ||
| + | |tbm=No | ||
| + | |bmi1=Yes | ||
| + | |bmi2=Yes | ||
| + | |fma3=Yes | ||
| + | |fma4=No | ||
| + | |aes=Yes | ||
| + | |rdrand=Yes | ||
| + | |sha=No | ||
| + | |xop=No | ||
| + | |adx=Yes | ||
| + | |clmul=Yes | ||
| + | |f16c=Yes | ||
| + | |tbt1=No | ||
| + | |tbt2=Yes | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=Yes | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |ivmd=Yes | ||
| + | |intelnodecontroller=Yes | ||
| + | |intelnode=Yes | ||
| + | |kpt=Yes | ||
| + | |ptt=Yes | ||
| + | |intelrunsure=Yes | ||
| + | |mbe=Yes | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=Yes | ||
| + | |txt=Yes | ||
| + | |ht=Yes | ||
| + | |vpro=Yes | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
| }} | }} | ||
Revision as of 04:18, 12 July 2017
Template:mpu Xeon Platinum 8160F is a 64-bit 24-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8160F, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 160 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Contents
Cache
- Main article: Skylake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
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Memory controller
|  | Integrated Memory Controller | |||||||||||||
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Expansions
|  | Expansion Options | |||||||
| 
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Features
[Edit/Modify Supported Features]
|  | Supported x86 Extensions & Processor Features | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 
 
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Facts about "Xeon Platinum 8160F  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Platinum 8160F - Intel#io + | 
| base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + | 
| chipset | Lewisburg + | 
| clock multiplier | 21 + | 
| core count | 24 + | 
| core family | 6 + | 
| core name | Skylake SP + | 
| core stepping | H0 + | 
| cpuid | 0x50654 + | 
| designer | Intel + | 
| family | Xeon Platinum + | 
| first announced | July 11, 2017 + | 
| first launched | July 11, 2017 + | 
| full page name | intel/xeon platinum/8160f + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has advanced vector extensions 512 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + | 
| has intel enhanced speedstep technology | true + | 
| has intel speed shift technology | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + | 
| ldate | July 11, 2017 + | 
| main image |  + | 
| manufacturer | Intel + | 
| market segment | Server + | 
| max case temperature | 360.15 K (87 °C, 188.6 °F, 648.27 °R) + | 
| max cpu count | 8 + | 
| max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| max pcie lanes | 48 + | 
| microarchitecture | Skylake (server) + | 
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + | 
| min dts temperature | 0 °C + | 
| model number | 8160F + | 
| name | Xeon Platinum 8160F + | 
| package | FCLGA-3647 + | 
| part number | CD8067303593600 + | 
| platform | Purley + | 
| process | 14 nm (0.014 μm, 1.4e-5 mm) + | 
| release price | $ 4,856.00 (€ 4,370.40, £ 3,933.36, ¥ 501,770.48) + | 
| s-spec | SR3KG + | 
| s-spec (qs) | QN3E + | 
| series | 8000 + | 
| smp max ways | 8 + | 
| socket | Socket P + and LGA-3647 + | 
| supported memory type | DDR4-2666 + | 
| tdp | 160 W (160,000 mW, 0.215 hp, 0.16 kW) + | 
| technology | CMOS + | 
| thread count | 48 + | 
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + |