Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon bronze/3104"
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Revision as of 13:25, 11 July 2017
Template:mpu Xeon Bronze 3104 is a 64-bit hexa-core x86 dual-socket entry-level server and workstation microprocessor introduced by Intel in mid-2017. The Bronze 3104, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
Contents
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon Bronze 3104 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Bronze 3104 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 + and Advanced Encryption Standard Instruction Set Extension + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
| max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
| max memory channels | 6 + |
| max pcie lanes | 48 + |
| supported memory type | DDR4-2133 + |