Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon bronze/3104"
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Revision as of 01:41, 11 July 2017
Template:mpu Xeon Bronze 3104 is a 64-bit hexa-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 1.7 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Bronze 3104 - Intel"
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |