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Difference between revisions of "arm holdings/microarchitectures/arm6"
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=== Key changes from {{\\|ARM3}} === | === Key changes from {{\\|ARM3}} === | ||
| + | * 32-bit address space (from {{arm|26-bit}}) | ||
| + | ** Can map 4 GiB of memory | ||
| + | ** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]] | ||
| + | ** Their own separate registers | ||
| + | * New Modes | ||
| + | ** Abort (abt) | ||
| + | ** Undefined (und) | ||
| + | * Virtual memory | ||
| + | ** Integrated [[MMU]] | ||
== Die == | == Die == | ||
Revision as of 14:05, 2 July 2017
| Edit Values | |
| ARM6 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | VLSI Technology, GEC-Plessey Semiconductors |
| Introduction | 1993 |
| Process | 0.8 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Scalar, Pipelined |
| Stages | 3 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv3 |
| Cache | |
| L1 Cache | 4 KiB/core 64-way set associative |
| Succession | |
ARM6 is an ARM microarchitecture designed by ARM Holdings and introduced in 1993 as a successor to the ARM3. This was the first design by ARM as an independent company.
Contents
History
 |
This section is empty; you can help add the missing info by editing this page. |
Process Technology
- See also: 0.8 µm process
The ARM6 was implemented on a 0.8 µm CMOS process.
Architecture
Key changes from ARM3
- 32-bit address space (from 26-bit)
- Can map 4 GiB of memory
- CPSR & SPSR moved out of the program counter
- Their own separate registers
- New Modes
- Abort (abt)
- Undefined (und)
- Virtual memory
- Integrated MMU
Die
ARM6 MacroCell
- 3.1 mm x 1.9 mm
- 5.89 mm² die size
- 54 mW @ 20 MHz @ 3 Volt
- 0.8 µm CMOS
- 35,530 transistors
ARM610
- 26.45 mm² die size
- 358,931 transistors
- TQFP-144
All ARM6 Chips
| List of ARM6-based Processors | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Model | Manufacturer | Core | Launched | Frequency | Power Dissipation | Max Memory | ||||||
| VY86C060 | VLSI Technology | ARM60 | 1993 | 20 MHz 0.02 GHz , 25 MHz20,000 kHz 0.025 GHz 25,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C06020 | VLSI Technology | ARM60 | 1994 | 20 MHz 0.02 GHz 20,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C06040 | VLSI Technology | ARM60 | 1994 | 40 MHz 0.04 GHz 40,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C060A | VLSI Technology | ARM60 | 1994 | 33 MHz 0.033 GHz 33,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C061 | VLSI Technology | ARM60 | 1993 | 20 MHz 0.02 GHz , 25 MHz20,000 kHz 0.025 GHz 25,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C610 | VLSI Technology | ARM610 | 1993 | 20 MHz 0.02 GHz , 25 MHz20,000 kHz 0.025 GHz 25,000 kHz | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | |||||||
| VY86C610C | VLSI Technology | ARM610 | 23 July 1994 | 33 MHz 0.033 GHz 33,000 kHz | 0.5 W 500 mW 6.705e-4 hp 5.0e-4 kW | 4 GiB 4,096 MiB 4,194,304 KiB 4,294,967,296 B 0.00391 TiB | ||||||
| Count: 7 | ||||||||||||
References
- Muller, Mike. "ARM6: a high performance low power consumption macrocell." Compcon Spring'93, Digest of Papers.. IEEE, 1993.
Facts about "ARM6 - Microarchitectures - ARM"
| codename | ARM6 + |
| core count | 1 + |
| designer | ARM Holdings + |
| first launched | 1993 + |
| full page name | arm holdings/microarchitectures/arm6 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv3 + |
| manufacturer | VLSI Technology + and GEC-Plessey Semiconductors + |
| microarchitecture type | CPU + |
| name | ARM6 + |
| pipeline stages | 3 + |
| process | 800 nm (0.8 μm, 8.0e-4 mm) + |