Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/cores/silverthorne"
(→Overview) |
|||
| Line 36: | Line 36: | ||
* '''Tech:''' All models have {{intel|EIST}} | * '''Tech:''' All models have {{intel|EIST}} | ||
* '''Bus:''' 400-533 MHz [[FSB]] | * '''Bus:''' 400-533 MHz [[FSB]] | ||
| + | * {{intel|Poulsbo|l=chipset}} Chipset | ||
* 47,212,207 transistors | * 47,212,207 transistors | ||
* 24.2 mm² die size (3.1 mm x 7.8 mm) | * 24.2 mm² die size (3.1 mm x 7.8 mm) | ||
Revision as of 18:56, 27 March 2017
| Edit Values | |
| Silverthorne | |
 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | April 2, 2008 (announced) April 2, 2008 (launched) |
| Microarchitecture | |
| ISA | x86-32 |
| Microarchitecture | Bonnell |
| Word Size | 32 bit 324 octets 8 nibbles |
| Process | 45 nm 0.045 μm 4.5e-5 mm |
| Technology | CMOS |
| Clock | 800 MHz - 2,133.33 MHz |
Silverthorne is the core name for Intel's first generation of Atom processors based on the Bonnell microarchitecture. Those ultra-low power chips were manufactured on Intel's 45 nm process and were specifically aimed for the Mobile Internet device (MID) market. Silverthorne-based processors are 32-bit x86 single core processors with TDP ranging from just 650 mW to 2.5 W.
Overview
All models are based on Bonnell manufactured on a 45 nm process and implement x86-32 with no 64-bit support.
- TDP: 650 mW - 2.5 W
- ISA: Everything up to SSSE3 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3)
- Tech: All models have EIST
- Bus: 400-533 MHz FSB
- Poulsbo Chipset
- 47,212,207 transistors
- 24.2 mm² die size (3.1 mm x 7.8 mm)
Members
 |
This section is empty; you can help add the missing info by editing this page. |
See Also
Facts about "Silverthorne - Cores - Intel"
| designer | Intel + |
| first announced | April 2, 2008 + |
| first launched | April 2, 2008 + |
| instance of | core + |
| isa | x86-32 + |
| main image | + |
| manufacturer | Intel + |
| microarchitecture | Bonnell + |
| name | Silverthorne + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
