Semiconductor & Computer Engineering
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Difference between revisions of "loongson/godson 2/2c"
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| core stepping = | | core stepping = | ||
| process = 180 nm | | process = 180 nm | ||
| − | | transistors = | + | | transistors = 13,500,000 |
| technology = CMOS | | technology = CMOS | ||
| die area = 41.54 mm² | | die area = 41.54 mm² | ||
Revision as of 18:04, 19 March 2017
Template:mpu Godson-2C (龙芯2C) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late 2004, the Godson-2C operates at up to 500 MHz consuming 3-5W. This chip was manufactured on SMICS' 0.18 µm process.
The Godson-2C provides roughly three times the performance of 2B. The 2C has twice the cache and almost twice the frequency as the 2B, along with an improved branch predictor.
Cache
- Main article: GS464 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Godson-2C - Loongson"
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |