Semiconductor & Computer Engineering
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Difference between revisions of "amd/athlon mp/amp1800dms3c"
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | | + | |protected=Yes |
| − | | 3dnow | + | |smm=Yes |
| − | | e3dnow | + | |fpu=Yes |
| − | | sse | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| + | |x8664=No | ||
| + | |nx=No | ||
| + | |3dnow=Yes | ||
| + | |e3dnow=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=No | ||
| + | |sse3=No | ||
| + | |ssse3=No | ||
| + | |sse41=No | ||
| + | |sse42=No | ||
| + | |sse4a=No | ||
| + | |avx=No | ||
| + | |avx2=No | ||
| + | |avx512=No | ||
| + | |abm=No | ||
| + | |tbm=No | ||
| + | |bmi1=No | ||
| + | |bmi2=No | ||
| + | |fma3=No | ||
| + | |fma4=No | ||
| + | |aes=No | ||
| + | |rdrand=No | ||
| + | |sha=No | ||
| + | |xop=No | ||
| + | |adx=No | ||
| + | |clmul=No | ||
| + | |f16c=No | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=No | ||
| + | |flex=No | ||
| + | |isrt=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=No | ||
| + | |ht=No | ||
| + | |vpro=No | ||
| + | |vtx=No | ||
| + | |vtd=No | ||
| + | |ept=No | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |smartmp=Yes | ||
| + | |powernow=No | ||
| + | |amdv=No | ||
| + | |rvi=No | ||
}} | }} | ||
* Advanced Configuration and Power Interface [[has feature::ACPI| ]] | * Advanced Configuration and Power Interface [[has feature::ACPI| ]] | ||
Revision as of 05:29, 26 November 2016
Template:mpu The Athlon MP 1800+ (OPN AMP1800DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.53 GHz with a FSB transfer rate of 266 MT/s (x11.5 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 16-way set associative |
Graphics
This MPU has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 1800+ - AMD"
| has amd smartmp technology | true + |
| has feature | SmartMP Technology +, ACPI +, Halt State + and Stop Grant State + |
| has multiprocessing support | true + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |