Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/athlon mp/ahx1200dhs3c"
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | | + | |protected=Yes |
| − | | 3dnow | + | |smm=Yes |
| − | | e3dnow | + | |fpu=Yes |
| − | | sse | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| + | |x8664=No | ||
| + | |nx=No | ||
| + | |3dnow=Yes | ||
| + | |e3dnow=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=No | ||
| + | |sse3=No | ||
| + | |ssse3=No | ||
| + | |sse41=No | ||
| + | |sse42=No | ||
| + | |sse4a=No | ||
| + | |avx=No | ||
| + | |avx2=No | ||
| + | |avx512=No | ||
| + | |abm=No | ||
| + | |tbm=No | ||
| + | |bmi1=No | ||
| + | |bmi2=No | ||
| + | |fma3=No | ||
| + | |fma4=No | ||
| + | |aes=No | ||
| + | |rdrand=No | ||
| + | |sha=No | ||
| + | |xop=No | ||
| + | |adx=No | ||
| + | |clmul=No | ||
| + | |f16c=No | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=No | ||
| + | |flex=No | ||
| + | |isrt=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=No | ||
| + | |ht=No | ||
| + | |vpro=No | ||
| + | |vtx=No | ||
| + | |vtd=No | ||
| + | |ept=No | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |smartmp=Yes | ||
| + | |powernow=No | ||
| + | |amdv=No | ||
| + | |rvi=No | ||
}} | }} | ||
* Advanced Configuration and Power Interface [[has feature::ACPI| ]] | * Advanced Configuration and Power Interface [[has feature::ACPI| ]] | ||
Revision as of 05:29, 26 November 2016
Template:mpu Athlon MP 1200 (OPN AHX1200DHS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in 2001 for the server and workstation market. This low-voltage model operated at 1.2 GHz with a FSB transfer rate of 266 MT/s. This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 16-way set associative |
Graphics
This MPU has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 6 Data Sheet Multiprocessor-Capable for Workstation and Server Platforms; Publication # 24685; Rev.: B; Issue Date: June 2001.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 1200 - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Athlon MP 1200 - AMD#package + |
| base frequency | 1,200 MHz (1.2 GHz, 1,200,000 kHz) + |
| bus rate | 266 MT/s (0.266 GT/s, 266,000 kT/s) + |
| bus speed | 133 MHz (0.133 GHz, 133,000 kHz) + |
| bus type | FSB + |
| chipset | AMD-760MP + |
| clock multiplier | 9 + |
| core count | 1 + |
| core family | 6 + |
| core model | 6 + |
| core name | Palomino + |
| core stepping | 2 + |
| core voltage | 1.55 V (15.5 dV, 155 cV, 1,550 mV) + |
| cpuid | 662 + |
| designer | AMD + |
| die area | 128 mm² (0.198 in², 1.28 cm², 128,000,000 µm²) + |
| family | Athlon MP + |
| first announced | June 5, 2001 + |
| first launched | June 5, 2001 + |
| full page name | amd/athlon mp/ahx1200dhs3c + |
| has amd smartmp technology | true + |
| has feature | SmartMP Technology +, ACPI +, Halt State + and Stop Grant State + |
| has locked clock multiplier | true + |
| has multiprocessing support | true + |
| instance of | microprocessor + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | June 5, 2001 + |
| manufacturer | AMD + |
| market segment | Server + |
| max case temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
| max cpu count | 2 + |
| max junction temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
| microarchitecture | K7 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
| model number | Athlon MP 1200 + |
| name | AMD Athlon MP 1200 + |
| package | OPGA-453 + |
| part number | AHX1200DHS3C + |
| platform | Athlon MP + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| release price | $ 265.00 (€ 238.50, £ 214.65, ¥ 27,382.45) + |
| smp max ways | 2 + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 37,500,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |