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(Memory Hierarchy)
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** L2 Cache:
 
** L2 Cache:
 
*** 512 KB 8-way set associative
 
*** 512 KB 8-way set associative
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*** ECC
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*** Shrinkable from 512 KB to 128 KB (2-way)
 
*** Per core
 
*** Per core
 
** L3 Cache:
 
** L3 Cache:
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Note that the L1 cache for data and instructions were originally both 32 KB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KB.
 
Note that the L1 cache for data and instructions were originally both 32 KB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KB.
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=== Functional Units ===
 
=== Functional Units ===
 
The number of functional units were kept to minimum to cut on power consumption.
 
The number of functional units were kept to minimum to cut on power consumption.

Revision as of 15:38, 7 April 2016

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Bonnell µarch
General Info
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Bonnell was a microarchitecture for Intel's 45 nm ultra-low power microprocessors first introduced in 2008 for their then-new Atom family. Bonnell, which was named after the highest point in Austin - Mount Bonnell, was Intel's first x86-compatible microarchitecture designed to target the ultra-low power market.

Architecture

Bonnell's primary goals were:

  1. Reduce power consumption,
  2. while staying fully x86-compatible,
  3. at acceptable performance

Performance/Power new rule: +1% performance for at most +1% power consumption.

Memory Hierarchy

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KB 8-way set associative instruction
        • 1 read and 1 write port
      • 24 KB 6-way set associative data
        • 1 read and 1 write port
      • Per core
    • L2 Cache:
      • 512 KB 8-way set associative
      • ECC
      • Shrinkable from 512 KB to 128 KB (2-way)
      • Per core
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 2 GB, 4 GB, and 8 GB

Note that the L1 cache for data and instructions were originally both 32 KB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KB.

Functional Units

The number of functional units were kept to minimum to cut on power consumption.

  • 2 Integer ALUs (1 for jumps, 1 for shifts)
  • 2 FP ALUs (1 adder, 1 for others)
  • No Integer multiplier & divider

Pipeline

Much like other x86 microarchitectures, Bonnell converts the complex instructions into finer micro-ops. Bonnell has a 16-stage pipeline with a 13-stage miss penalty. Bonnell is a dual-issue superscalar but with in-order execution (in fact, first microarchitecture since Pentium Pro to not feature a OoOE). The elimination of reordering logic allowed for lower power consumption and small die area. This does imply the overall MPU is less efficient in managing its own resources; memory accesses and FP operations also stall the whole pipeline. Bonnell employed Safe Instruction Recognition (SIR) and Simultaneous multithreading (SMT) to bring performance to acceptable level. Intel claimed sub-20% power consumption penalty while improving performance between 30% and 50%.

Cores

First generation of Bonnel-based microprocessors introduced 2 cores: Silverthorne for ultra-mobile PCs and mobile Internet devices (MIDs) and Diamondville for ultra cheap notebooks and desktops.

Silverthorne

Main article: Silverthorne

Silverthorne was the codename for a series of ultra-mobile PCs introduced in 2008.

Key features:

  • 32-bit
  • 1 Core / 2 Threads
  • FSB 400 MHz - 533 MHz
  • Cache
    • 32 KB L1i$ / 23 KB L1d$
    • 512 KB L2$
    • No L3$

Diamondville

Main article: Diamondville

Diamondville was the codename for the series of ultra cheap notebooks and desktops introduced in 2008. Diamondville is very much a derivative of Silverthorne with faster FSB.

Key features:

  • 32-bit
  • 1 Core / 2 Threads
  • FSB 533 MHz - 667 MHz
  • Cache
    • 32 KB L1i$ / 23 KB L1d$ (per core)
    • 512 KB L2$ (per core)
    • No L3$