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Difference between revisions of "Template:logic gate"

(initial layout idea)
 
Line 53: Line 53:
 
| [[MUX]] || [[DEMUX]] || [[encoder (circuit)|Encoder]]
 
| [[MUX]] || [[DEMUX]] || [[encoder (circuit)|Encoder]]
 
|-
 
|-
−
| [[decoder (circuit)|Decoder]]
+
| [[decoder (circuit)|Decoder]] || [[priority encoder|Pri-Encoder]]
 
|-
 
|-
 
! colspan="3" | [[ALU]]
 
! colspan="3" | [[ALU]]
Line 61: Line 61:
 
| [[Divider]] || [[Shifter]] || [[Rotator]]
 
| [[Divider]] || [[Shifter]] || [[Rotator]]
 
|-
 
|-
−
| [[Comparator]]
+
| [[Comparator]] || [[Negator]]
−
|  
+
|-
 +
! colspan="3" | Memory
 +
|-
 +
| [[D latch]] || [[D flip-flop]] || [[SR latch]]
 +
|-
 +
| [[JK flip-flop]] || [[T flip-flop]] || [[Register]]
 +
|-
 +
| [[Register file]] || [[SRAM]] || [[Counter]]
 +
|-
 +
| [[ROM]] || [[CAM]] || [[DRAM]]
 +
|-
 +
! colspan="3" | I/O
 +
|-
 +
| [[Shift register]] || [[SIPO]] || [[PISO]]
 
|}
 
|}
 
|}
 
|}
 
|}
 
|}

Revision as of 13:39, 21 November 2015

AND Gate
ANSI Symbol
and gate (ansi).svg
Functional
and gate functional.gif
Truth Table
Inputs Outputs
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
Other Gates
Buffer Tri-state Buffer NOT
AND OR XOR
NAND NOR XNOR
IMPLY NIMPLY INH
Other Components
Plexers
MUX DEMUX Encoder
Decoder Pri-Encoder
ALU
Adder Subtractor Multiplier
Divider Shifter Rotator
Comparator Negator
Memory
D latch D flip-flop SR latch
JK flip-flop T flip-flop Register
Register file SRAM Counter
ROM CAM DRAM
I/O
Shift register SIPO PISO
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