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Difference between revisions of "cavium/thunderx2/cn9980"
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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|model number=CN9980
 
|model number=CN9980
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|part number=CN9980-2500LG4077-Y21-G
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|part number=CN9980-2500<!--LG4077-Y21-G-->
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|part number 2=CN9980-2400LG4077-Y21-G
+
|part number 2=CN9980-2400<!--LG4077-Y21-G-->
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|part number 3=CN9980-2300LG4077-Y21-G
+
|part number 3=CN9980-2300<!--LG4077-Y21-G-->
−
|part number 4=CN9980-2200LG4077-Y21-G
+
|part number 4=CN9980-2200<!--LG4077-Y21-G-->
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|part number 5=CN9980-2100LG4077-Y21-G
+
|part number 5=CN9980-2100<!--LG4077-Y21-G-->
−
|part number 6=CN9980-2000LG4077-Y21-G
+
|part number 6=CN9980-2000<!--LG4077-Y21-G-->
 
|market=Server
 
|market=Server
 
|first announced=May 7, 2018
 
|first announced=May 7, 2018
 
|first launched=May 7, 2018
 
|first launched=May 7, 2018
 
|family=ThunderX2
 
|family=ThunderX2
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|frequency=2,000 MHz
+
|frequency=2.5 GHz
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|frequency 2=2,100 MHz
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|frequency 2=2.0 GHz
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|frequency 3=2,200 MHz
 
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|frequency 4=2,300 MHz
 
 
|isa=ARMv8.1
 
|isa=ARMv8.1
 
|isa family=ARM
 
|isa family=ARM
Line 32: Line 30:
 
|package name 1=cavium,fclga_4077
 
|package name 1=cavium,fclga_4077
 
}}
 
}}
−
'''ThunderX2 CN9980''' is a {{arch|64}} [[dotriaconta-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9978 operates between 2 GHz and 2.5 GHz and supports up to octa-channel DDR4-2666 memory.
 
  
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== Cache ==
+
'''ThunderX2 CN9980''' is a {{arch|64}} [[dotriaconta-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]].
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{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
 
−
{{cache size
 
−
|l1 cache=2 MiB
 
−
|l1i cache=1 MiB
 
−
|l1i break=32x32 KiB
 
−
|l1i desc=8-way set associative
 
−
|l1d cache=1 MiB
 
−
|l1d break=32x32 KiB
 
−
|l1d desc=8-way set associative
 
−
|l2 cache=8 MiB
 
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|l2 break=32x256 KiB
 
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|l2 desc=8-way set associative
 
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|l3 cache=32 MiB
 
−
|l3 break=32x1 MiB
 
−
}}
 
  
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== Memory controller ==
+
Depending on the exact SKU, the CN9980 operates between 2 GHz and 2.5 GHz and supports up to octa-channel DDR4-2666 memory.
−
{{memory controller
 
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|type=DDR4-2666
 
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|ecc=Yes
 
−
|max mem=2 TiB
 
−
|controllers=2
 
−
|channels=8
 
−
|max bandwidth=158.95 GiB/s
 
−
|bandwidth schan=19.87 GiB/s
 
−
|bandwidth dchan=39.74 GiB/s
 
−
|bandwidth qchan=79.47 GiB/s
 
−
|bandwidth hchan=119.21 GiB/s
 
−
|bandwidth ochan=158.95 GiB/s
 
−
}}
 
  
 
== Expansions ==
 
== Expansions ==
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|wmmx=No
 
|wmmx=No
 
|wmmx2=No
 
|wmmx2=No
−
|pmuv3=No
+
|pmuv3=Yes
 
|crc32=Yes
 
|crc32=Yes
 
|crypto=Yes
 
|crypto=Yes
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|fp=No
+
|fp=Yes
 
|fp16=No
 
|fp16=No
 
|profile=No
 
|profile=No
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|rdm=No
 
|rdm=No
 
}}
 
}}
 +
 +
== Cache ==
 +
{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
 +
{{cache size
 +
|l1 cache=2 MiB
 +
|l1i cache=1 MiB
 +
|l1i break=32x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1 MiB
 +
|l1d break=32x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=8 MiB
 +
|l2 break=32x256 KiB
 +
|l2 desc=8-way set associative
 +
|l3 cache=32 MiB
 +
|l3 break=32x1 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=2 TiB
 +
|controllers=2
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
}}
 +
 +
[[Category:cavium]]

Latest revision as of 12:46, 24 March 2025

Edit Values
ThunderX2 CN9980
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN9980
Part NumberCN9980-2500,
CN9980-2400,
CN9980-2300,
CN9980-2200,
CN9980-2100,
CN9980-2000
MarketServer
IntroductionMay 7, 2018 (announced)
May 7, 2018 (launched)
General Specs
FamilyThunderX2
Frequency2.5 GHz, 2.0 GHz
Microarchitecture
ISAARMv8.1 (ARM)
MicroarchitectureVulcan
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads128
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Packaging
PackageFCLGA-4077 (LGA)
Contacts4077

ThunderX2 CN9980 is a 64-bit dotriaconta-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process.

Depending on the exact SKU, the CN9980 operates between 2 GHz and 2.5 GHz and supports up to octa-channel DDR4-2666 memory.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 56
Configuration: x16, x8, x4, x1
SATARevision: 3
Max Ports: 2
USBRevision: 3
Max Ports: 2


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
PMUv3ARMv8 PMUv3 Performance Monitors Extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension
SIMDAdvanced SIMD extension

Cache[edit]

Main article: Vulcan § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2 MiB
2,048 KiB
2,097,152 B
L1I$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers2
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/thunderx2/cn9980&oldid=103059"
Facts about "ThunderX2 CN9980 - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
ThunderX2 CN9980 - Cavium#pcie +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) + and 2,000 MHz (2 GHz, 2,000,000 kHz) +
core count32 +
designerCavium +
familyThunderX2 +
first announcedMay 7, 2018 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2/cn9980 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8.1 +
isa familyARM +
l1$ size2,048 KiB (2,097,152 B, 2 MiB) +
l1d$ description8-way set associative +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description8-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateMay 7, 2018 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max sata ports2 +
max usb ports2 +
microarchitectureVulcan +
model numberCN9980 +
nameThunderX2 CN9980 +
packageFCLGA-4077 +
part numberCN9980-2500 +, CN9980-2400 +, CN9980-2300 +, CN9980-2200 +, CN9980-2100 + and CN9980-2000 +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
supported memory typeDDR4-2666 +
technologyCMOS +
thread count128 +
word size64 bit (8 octets, 16 nibbles) +