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'''AWS Graviton3''' is a [[tetrahexaconta-core]] [[ARMv8]] microprocessor designed by [[Amazon]] ([[Annapurna Labs]]) for Amazon's own infrastructure. Graviton3 is a [[5 nm]] 7-chiplet design SoC based on the Arm [[CMN-650 mesh interconnect]] and [[Neoverse V1]] core microarchitecture. This chip supports octa-channel DDR5-4800 ECC memory along with 32 lanes of PCIe 5.0.
 
'''AWS Graviton3''' is a [[tetrahexaconta-core]] [[ARMv8]] microprocessor designed by [[Amazon]] ([[Annapurna Labs]]) for Amazon's own infrastructure. Graviton3 is a [[5 nm]] 7-chiplet design SoC based on the Arm [[CMN-650 mesh interconnect]] and [[Neoverse V1]] core microarchitecture. This chip supports octa-channel DDR5-4800 ECC memory along with 32 lanes of PCIe 5.0.
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== Cache ==
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{{main|arm_holdings/microarchitectures/neoverse v1#Memory_Hierarchy|l1=Neoverse V1 § Cache}}
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{{cache size
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|l1 cache=8 MiB
 +
|l1i cache=4 MiB
 +
|l1i break=64x64 KiB
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|l1d cache=4 MiB
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|l1d break=64x64 KiB
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|l2 cache=64 MiB
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|l2 break=64x1 MiB
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|l3 cache=32 MiB
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|l3 break=1x32 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR5-4800
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|ecc=Yes
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|controllers=4
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|channels=8
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|max bandwidth=307.2 GB/s
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|bandwidth schan=38.4 GB/s
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|bandwidth dchan=76.8 GB/s
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|bandwidth qchan=153.6 GB/s
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|bandwidth ochan=307.2 GB/s
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}}
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== Expansions ==
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{{expansions
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| pcie revision      = 5.0
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| pcie lanes        = 32
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| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}

Revision as of 01:23, 12 December 2023

Edit Values
AWS Graviton3
graviton3.png
Graviton3 Package Front
graviton3(2).png
General Info
DesignerAnnapurna Labs
ManufacturerTSMC
MarketServer
IntroductionNovember 30, 2021 (announced)
November 30, 2021 (launched)
General Specs
FamilyGraviton
Frequency2,600 MHz
Microarchitecture
ISAARMv8.4-A (ARM)
MicroarchitectureNeoverse V1
Process5 nm
Transistors55,000,000,000
TechnologyCMOS
MCPYes (7 dies)
Word Size64 bit
Cores64
Threads64
Succession
Contemporary
Graviton3E

AWS Graviton3 is a tetrahexaconta-core ARMv8 microprocessor designed by Amazon (Annapurna Labs) for Amazon's own infrastructure. Graviton3 is a 5 nm 7-chiplet design SoC based on the Arm CMN-650 mesh interconnect and Neoverse V1 core microarchitecture. This chip supports octa-channel DDR5-4800 ECC memory along with 32 lanes of PCIe 5.0.


Cache

Main article: Neoverse V1 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$8 MiB
8,192 KiB
8,388,608 B
L1I$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L1D$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L2$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  64x1 MiB  
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  1x32 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-4800
Supports ECCYes
Controllers4
Channels8
Max Bandwidth307.2 GB/s
286.102 GiB/s
292,968.75 MiB/s
307,200 MB/s
0.279 TiB/s
0.307 TB/s
Bandwidth
Single 38.4 GB/s
Double 76.8 GB/s
Quad 153.6 GB/s
Octa 307.2 GB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision5.0
Max Lanes32
Configsx16, x8, x4
Retrieved from "https://en.wikichip.org/w/index.php?title=annapurna_labs/graviton/graviton3&oldid=102074"
Facts about "AWS Graviton3 - Annapurna Labs (Amazon)"
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AWS Graviton3 - Annapurna Labs (Amazon)#io +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
core count64 +
designerAnnapurna Labs +
die count7 +
familyGraviton +
first announcedNovember 30, 2021 +
first launchedNovember 30, 2021 +
full page nameannapurna labs/graviton/graviton3 +
has ecc memory supporttrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isaARMv8.4-A +
isa familyARM +
l1$ size8,192 KiB (8,388,608 B, 8 MiB) +
l1d$ size4,096 KiB (4,194,304 B, 4 MiB) +
l1i$ size4,096 KiB (4,194,304 B, 4 MiB) +
l2$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateNovember 30, 2021 +
main imageFile:graviton3.png +
main image captionGraviton3 Package Front +
manufacturerTSMC +
market segmentServer +
max memory bandwidth286.102 GiB/s (292,968.75 MiB/s, 307.2 GB/s, 307,200 MB/s, 0.279 TiB/s, 0.307 TB/s) +
max memory channels8 +
max pcie lanes32 +
microarchitectureNeoverse V1 +
nameAWS Graviton3 +
process5 nm (0.005 μm, 5.0e-6 mm) +
supported memory typeDDR5-4800 +
technologyCMOS +
thread count64 +
transistor count55,000,000,000 +
word size64 bit (8 octets, 16 nibbles) +