(Replaced package module by package name.) |
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Line 11: | Line 11: | ||
|first announced=February 21, 2018 | |first announced=February 21, 2018 | ||
|first launched=February 21, 2018 | |first launched=February 21, 2018 | ||
+ | |last order=2028 | ||
|family=EPYC Embedded | |family=EPYC Embedded | ||
|series=3000 | |series=3000 | ||
+ | |locked=Yes | ||
|frequency=1,500 MHz | |frequency=1,500 MHz | ||
|turbo frequency1=3,100 MHz | |turbo frequency1=3,100 MHz | ||
Line 23: | Line 25: | ||
|core family=23 | |core family=23 | ||
|core model=1 | |core model=1 | ||
+ | |core stepping=B2 | ||
+ | |cpuid=0x00800F12 | ||
|process=14 nm | |process=14 nm | ||
|transistors=4,800,000,000 | |transistors=4,800,000,000 | ||
Line 35: | Line 39: | ||
|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=95 °C | |tjunc max=95 °C | ||
− | |package | + | |package name 1=amd,sp4r2 |
}} | }} | ||
− | '''EPYC Embedded 3201''' is a {{arch|64}} [[octa-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. | + | '''EPYC Embedded 3201''' is a {{arch|64}} [[octa-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[GlobalFoundries]] [[14 nm#GlobalFoundries|14 nm]] process. It operates at 1.5 GHz with a {{abbr|TDP}} of 30 W and a {{amd|precision boost|turbo frequency}} of up to 3.1 GHz. The 3201 supports up to 512 GiB of dual-channel DDR4-2133 memory. |
− | |||
== Cache == | == Cache == | ||
Line 45: | Line 48: | ||
|l1 cache=768 KiB | |l1 cache=768 KiB | ||
|l1i cache=512 KiB | |l1i cache=512 KiB | ||
− | |l1i break= | + | |l1i break=8 × 64 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1d cache=256 KiB | |l1d cache=256 KiB | ||
− | |l1d break= | + | |l1d break=8 × 32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
|l2 cache=4 MiB | |l2 cache=4 MiB | ||
− | |l2 break= | + | |l2 break=8 × 512 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
|l3 cache=16 MiB | |l3 cache=16 MiB | ||
− | |l3 break= | + | |l3 break=2 × 8 MiB |
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
Line 68: | Line 71: | ||
|controllers=2 | |controllers=2 | ||
|channels=2 | |channels=2 | ||
− | |max bandwidth= | + | |max bandwidth=34.13 GB/s |
− | |bandwidth schan= | + | |bandwidth schan=17.07 GB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=34.13 GB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | The EPYC Embedded 3201 | + | The EPYC Embedded 3201 integrates two 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to eight SATA ports and four GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: {{abbr|eMMC}}, {{abbr|UART}}, {{abbr|LPC}}, {{abbr|SPI/eSPI}}, {{abbr|I<sup>2</sup>C}}, {{abbr|SMBus}}, {{abbr|GPIO}}. |
+ | |||
{{expansions main | {{expansions main | ||
| | | | ||
Line 85: | Line 89: | ||
|pcie config 3=x4 | |pcie config 3=x4 | ||
|pcie config 4=x2 | |pcie config 4=x2 | ||
+ | |pcie config 5=x1 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=3.1 | ||
+ | |usb ports=4 | ||
}} | }} | ||
{{expansions entry | {{expansions entry | ||
Line 117: | Line 127: | ||
|sse42=Yes | |sse42=Yes | ||
|sse4a=Yes | |sse4a=Yes | ||
+ | |sse_gfni=No | ||
|avx=Yes | |avx=Yes | ||
+ | |avx_gfni=No | ||
|avx2=Yes | |avx2=Yes | ||
− | + | |avx512f=No | |
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512gfni=No | ||
+ | |avx512vaes=No | ||
+ | |avx512vbmi2=No | ||
+ | |avx512bitalg=No | ||
+ | |avx512vpclmulqdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 133: | Line 162: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=No | |tbt2=No | ||
|tbmt3=No | |tbmt3=No | ||
+ | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=No | |eist=No | ||
Line 141: | Line 172: | ||
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 158: | Line 196: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 168: | Line 208: | ||
|amdsev=Yes | |amdsev=Yes | ||
|rvi=No | |rvi=No | ||
− | |smt= | + | |smt=No |
|sensemi=Yes | |sensemi=Yes | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} | ||
+ | |||
+ | == Bibliography == | ||
+ | * [https://ir.amd.com/news-events/press-releases/detail/816/amd-launches-epyc-embedded-and-ryzen-embedded "AMD Launches EPYC™ Embedded and Ryzen™ Embedded Processors for End-to-End “Zen” Experiences from the Core to the Edge"] (Press release). AMD.com. February 21, 2018. | ||
+ | * {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|file=3000-Family-Product-Brief.pdf|publ=AMD|pid=1887102|date=2018}} | ||
+ | * {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|url=https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf|publ=AMD|pid=1887102|rev=E|date=2019}} | ||
+ | * [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. AMD.com. Retrieved October 2020. |
Latest revision as of 04:15, 24 March 2023
Edit Values | |
EPYC Embedded 3201 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 3201 |
Part Number | PE3201BHR88AF |
Market | Server, Embedded |
Introduction | February 21, 2018 (announced) February 21, 2018 (launched) |
End-of-life | 2028 (last order) |
Shop | Amazon |
General Specs | |
Family | EPYC Embedded |
Series | 3000 |
Locked | Yes |
Frequency | 1,500 MHz |
Turbo Frequency | 3,100 MHz (1 core), 3,100 MHz (8 cores) |
Clock multiplier | 15 |
CPUID | 0x00800F12 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Core Name | Snowy Owl |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B2 |
Process | 14 nm |
Transistors | 4,800,000,000 |
Technology | CMOS |
Die | 213 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 30 W |
Tjunction | 0 °C – 95 °C |
Packaging | |
Package | SP4r2 (FC-OBGA) |
Dimension | 45 mm × 45 mm |
Pitch | 0.8 mm |
EPYC Embedded 3201 is a 64-bit octa-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. This processor has CPU cores based on the Zen microarchitecture and is fabricated on a GlobalFoundries 14 nm process. It operates at 1.5 GHz with a TDP of 30 W and a turbo frequency of up to 3.1 GHz. The 3201 supports up to 512 GiB of dual-channel DDR4-2133 memory.
Cache[edit]
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
|
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Expansions[edit]
The EPYC Embedded 3201 integrates two 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to eight SATA ports and four GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: eMMC, UART, LPC, SPI/eSPI, I2C, SMBus, GPIO.
Expansion Options |
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Networking
|
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
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Bibliography[edit]
- "AMD Launches EPYC™ Embedded and Ryzen™ Embedded Processors for End-to-End “Zen” Experiences from the Core to the Edge" (Press release). AMD.com. February 21, 2018.
- "Product Brief: AMD EPYC™ Embedded 3000 Family", AMD Publ. #1887102, 2018
- "Product Brief: AMD EPYC™ Embedded 3000 Family", AMD Publ. #1887102, Rev. E, 2019
- "Embedded Processor Specifications". AMD.com. Retrieved October 2020.
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC Embedded 3201 - AMD#pcie + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
clock multiplier | 15 + |
core count | 8 + |
core family | 23 + |
core model | 1 + |
core name | Snowy Owl + |
core stepping | B2 + |
cpuid | 0x00800F12 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
family | EPYC Embedded + |
first announced | February 21, 2018 + |
first launched | February 21, 2018 + |
full page name | amd/epyc embedded/3201 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
last order | 2028 + |
ldate | February 21, 2018 + |
manufacturer | GlobalFoundries + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max junction temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 31.786 GiB/s (32,548.904 MiB/s, 34.13 GB/s, 34,130 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max sata ports | 8 + |
max usb ports | 4 + |
microarchitecture | Zen + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 3201 + |
name | EPYC Embedded 3201 + |
package | SP4r2 + |
part number | PE3201BHR88AF + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 3000 + |
smp max ways | 1 + |
supported memory type | DDR4-2133 + |
tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
technology | CMOS + |
thread count | 8 + |
transistor count | 4,800,000,000 + |
turbo frequency (1 core) | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
turbo frequency (8 cores) | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |