Difference between revisions of "amd/k6-iii+/amd-k6-iiie+-400icr"

	Edit Values
	AMD-K6-IIIE+/400ICR
	General Info
Designer	AMD
Manufacturer	AMD
Model Number	AMD-K6-IIIE+/400ICR
Part Number	AMD-K6-IIIE+/400ICR
Market	Embedded
Introduction	September 25, 2000 (announced); September 25, 2000 (launched)
Shop	Amazon
	General Specs
Family	K6-III+
Series	K6-III+ Embedded
Frequency	399.99 MHz
Bus type	FSB
Bus speed	99.99 MHz
Bus rate	99.99 MT/s
Clock multiplier	4
CPUID	5D0
	Microarchitecture
Microarchitecture	K6-III
Platform	Super 7
Core Family	5
Core Model	13
Core Stepping	0, 1, 2, 3
Process	0.18 µm
Transistors	21,400,000
Technology	CMOS
Word Size	32 bit
Cores	1
Threads	1
Max Memory	4 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	2.0 V ± 0.1 V
VI/O	3.3675 V ± 7%
TDP	9.5 W
Tcase	0 °C – 70 °C
Tstorage	-65 °C – 150 °C
	Packaging
Package	OBGA-349
Package Type	Organic Ball Grid Array
Dimension	25 mm × 25 mm
Pitch	1.27 mm
Contacts	349

Latest revision as of 12:42, 18 March 2023

AMD-K6-IIIE+/400ICR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.

Cache[edit]

Main article: K6-III § Cache

L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip.

Cache Info [Edit Values]
L1I$	32 KiB 32,768 B 0.0313 MiB	1x32 KiB 2-way set associative
L1D$	32 KiB 32,768 B 0.0313 MiB	1x32 KiB 2-way set associative
L2$	256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB	1x256 KiB 4-way set associative (shared)

Graphics[edit]

This processors has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
3DNow!	3DNow! Extension
E3DNow!	Extended 3DNow! Extension

Auto-power down state
Stop clock state
Halt state

@@ Line 1: / Line 1: @@
 {{amd title|AMD-K6-IIIE+/400ICR}}
-{{mpu
+{{chip
 | name                = AMD-K6-IIIE+/400ICR
 | no image            = Yes
@@ Line 10: / Line 10: @@
 | model number        = AMD-K6-IIIE+/400ICR
 | part number         = AMD-K6-IIIE+/400ICR
-| part number 1       =
 | part number 2       =
 | part number 3       =
+| part number 4       =
 | market              = Embedded
 | first announced     = September 25, 2000
@@ Line 49: / Line 49: @@
 | thread count        = 1
 | max cpus            = 1
-| max memory          = 4 GB
+| max memory          = 4 GiB
-| electrical          = Yes
 | power               =
 | v core              = 2.0 V
@@ Line 68: / Line 68: @@
 | tstorage max        = 150 °C
-| packaging           = Yes
+| package name 1      = amd,obga-349
-| package 0           = OBGA-349
-| package 0 type      = OBGA
-| package 0 pins      = 349
-| package 0 pitch     = 1.27 mm
-| package 0 width     = 25 mm
-| package 0 length    = 25 mm
-| package 0 height    = 1.41 mm
-| socket 0            = BGA-349
-| socket 0 type       = BGA
 }}
 '''AMD-K6-IIIE+/400ICR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
@@ Line 83: / Line 74: @@
 == Cache ==
 {{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}}
-[[L3$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip.
+[[L3$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip.
 {{cache info
-|l1i cache=32 KB
+|l1i cache=32 KiB
-|l1i break=1x32 KB
+|l1i break=1x32 KiB
 |l1i desc=2-way set associative
 |l1i extra=
-|l1d cache=32 KB
+|l1d cache=32 KiB
-|l1d break=1x32 KB
+|l1d break=1x32 KiB
 |l1d desc=2-way set associative
 |l1d extra=
-|l2 cache=256 KB
+|l2 cache=256 KiB
-|l2 break=1x256
+|l2 break=1x256 KiB
 |l2 desc=4-way set associative
 |l2 extra=(shared)
@@ Line 107: / Line 98: @@
 == Features ==
-{{mpu features
+{{x86 features
 | mmx         = Yes
 | emmx        = Yes

base frequency	399.99 MHz (0.4 GHz, 399,990 kHz) +
bus rate	99.99 MT/s (0.1 GT/s, 99,990 kT/s) +
bus speed	99.99 MHz (0.1 GHz, 99,990 kHz) +
bus type	FSB +
clock multiplier	4 +
core count	1 +
core family	5 +
core model	13 +
core stepping	0 +, 1 +, 2 + and 3 +
core voltage	2 V (20 dV, 200 cV, 2,000 mV) +
core voltage tolerance	0.1 V +
cpuid	5D0 +
designer	AMD +
family	K6-III+ +
first announced	September 25, 2000 +
first launched	September 25, 2000 +
full page name	amd/k6-iii+/amd-k6-iiie+-400icr +
instance of	microprocessor +
io voltage	3.368 V (33.675 dV, 336.75 cV, 3,367.5 mV) +
io voltage tolerance	7% +
l1d$ description	2-way set associative +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description	2-way set associative +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
l2$ description	4-way set associative +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate	September 25, 2000 +
manufacturer	AMD +
market segment	Embedded +
max case temperature	343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count	1 +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max storage temperature	423.15 K (150 °C, 302 °F, 761.67 °R) +
microarchitecture	K6-III +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	208.15 K (-65 °C, -85 °F, 374.67 °R) +
model number	AMD-K6-IIIE+/400ICR +
name	AMD-K6-IIIE+/400ICR +
package	OBGA-349 +
part number	AMD-K6-IIIE+/400ICR +
platform	Super 7 +
process	180 nm (0.18 μm, 1.8e-4 mm) +
series	K6-III+ Embedded +
smp max ways	1 +
tdp	9.5 W (9,500 mW, 0.0127 hp, 0.0095 kW) +
technology	CMOS +
thread count	1 +
transistor count	21,400,000 +
word size	32 bit (4 octets, 8 nibbles) +

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Latest revision as of 12:42, 18 March 2023

Cache[edit]

Graphics[edit]

Features[edit]