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Difference between revisions of "intel/xeon gold/5117"
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{{intel title|Xeon Gold 5117}} | {{intel title|Xeon Gold 5117}} | ||
− | {{ | + | {{chip |
|name=Xeon Gold 5117 | |name=Xeon Gold 5117 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5117 | |model number=5117 | ||
+ | |s-spec=SR37S | ||
|s-spec qs=QM8S | |s-spec qs=QM8S | ||
|market=Server | |market=Server | ||
Line 11: | Line 12: | ||
|first launched=July 11, 2017 | |first launched=July 11, 2017 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=5100 |
|locked=Yes | |locked=Yes | ||
|frequency=2,000 MHz | |frequency=2,000 MHz | ||
Line 19: | Line 20: | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 34: | Line 35: | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=81 °C | |tcase max=81 °C | ||
− | |package | + | |package name 1=intel,fclga_3647 |
+ | |successor=Xeon Gold 5217 | ||
+ | |successor link=intel/xeon_gold/5217 | ||
}} | }} | ||
− | '''Xeon Gold 5117''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5117, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | + | '''Xeon Gold 5117''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5117, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=896 KiB | |l1 cache=896 KiB | ||
Line 222: | Line 225: | ||
|freq_avx512_14=1,400 MHz | |freq_avx512_14=1,400 MHz | ||
}} | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 18:13, 3 August 2022
Edit Values | |
Xeon Gold 5117 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5117 |
S-Spec | SR37S QM8S (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 5100 |
Locked | Yes |
Frequency | 2,000 MHz |
Turbo Frequency | 2,800 MHz (1 core) |
Clock multiplier | 20 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 14 |
Threads | 28 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Electrical | |
TDP | 105 W |
Tcase | 0 °C – 81 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 5117 is a 64-bit tetradeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5117, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2 GHz with a TDP of 105 W and a turbo boost frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | ||
Normal | 2,000 MHz | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,300 MHz | 2,300 MHz |
AVX2 | 1,300 MHz | 2,800 MHz | 2,800 MHz | 2,500 MHz | 2,500 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz |
AVX512 | 1,100 MHz | 2,800 MHz | 2,800 MHz | 2,200 MHz | 2,200 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz |
Facts about "Xeon Gold 5117 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5117 - Intel#io + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 20 + |
core count | 14 + |
core family | 6 + |
core name | Skylake SP + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/5117 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
max cpu count | 4 + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 5117 + |
name | Xeon Gold 5117 + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR37S + |
s-spec (qs) | QM8S + |
series | 5100 + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 28 + |
turbo frequency (1 core) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |